An example test system includes robotics configured to operate on devices at a first level of precision, and stages configured to operate at levels of precision that are less than the first level of precision. Each of the stages may include parallel paths that are configured to pass the devices between adjacent stages.

An example test system includes robotics configured to operate on devices at a first level of precision, and stages configured to operate at levels of precision that are less than the first level of precision. Each of the stages may include parallel paths that are configured to pass the devices between adjacent stages.

A compensation device (20) for compensating for leakage currents has a differential current measuring device (22), a supply network detection device (42; 45), a control device (26), an amplifier (27), a compensation current selection device (36) and a feed-in device (39, 41). The supply network detection device (42; 45) generates a second signal (V_GRID; V_ES) characterizing the supply network (L1, L2, L3, N) connected to the active conductors (51, 52, 53, 54) and to supply it to the control device (26). The compensation current selection device (36) feeds in the compensation current (I_COMP) on the basis of a third signal (V_SEL) on at least one of the at least two different active conductors (51, 54), and the third signal (V_SEL) is dependent on the second signal (V_GRID; V_ES) to select at least one active conductor (51, 54) suitable for the connected supply network for the feed-in operation.

A compensation device (20) for compensating for leakage currents has a differential current measuring device (22), a supply network detection device (42; 45), a control device (26), an amplifier (27), a compensation current selection device (36) and a feed-in device (39, 41). The supply network detection device (42; 45) generates a second signal (V_GRID; V_ES) characterizing the supply network (L1, L2, L3, N) connected to the active conductors (51, 52, 53, 54) and to supply it to the control device (26). The compensation current selection device (36) feeds in the compensation current (I_COMP) on the basis of a third signal (V_SEL) on at least one of the at least two different active conductors (51, 54), and the third signal (V_SEL) is dependent on the second signal (V_GRID; V_ES) to select at least one active conductor (51, 54) suitable for the connected supply network for the feed-in operation.

According to an embodiment, an inspection apparatus inspects an inverter circuit including three pairs of arms. The apparatus includes a current controller and a control signal generator. The current controller generates a control output for controlling a current to be output by the inverter circuit. The control output enables the current to approach a target value of the current. The control signal generator generates a first control signal for controlling ON/OFF of a first arm as one of the three pairs of arms based on the control output, a second control signal for fixing a second arm paired with the first arm, in an OFF-state, and a third control signal for fixing at least part of arms other than the first arm and the second arm in an ON-state.

There is provided an intermediate connection member which is provided between a first member having a plurality of first terminals and a second member having a plurality of second terminals and electrically connects the plurality of first terminals and the plurality of second terminals, respectively, the intermediate connection member including: a pogo block including a main body and a plurality of pogo pins provided in the main body, the pogo block configured to connect the plurality of first terminals and the plurality of second terminals, respectively; and a pogo frame having an insertion hole into which the pogo block is inserted, wherein the pogo block has a positioning pin, and the pogo frame has a positioning hole into which the positioning pin is inserted, and wherein the pogo block is positioned with respect to the pogo frame when the positioning pin is inserted into the positioning hole.

A GFCI latching apparatus and circuit is provided. The latching apparatus includes a solenoid; a solenoid plunger, wherein the solenoid plunger comprises a groove; a conical spring disposed at one end of the solenoid plunger; a forked latch, wherein the forked latch engages the groove with its forks. The latch also includes a bevel surface. Also included is a contact carrier having a first position when the solenoid is energized and a second position when the solenoid is deenergized. The contact carrier includes a bevel surface for mating with the latch bevel surface when the solenoid is energized. Also included is a GFCI configured to deenergize the solenoid upon the occurrence of a fault to disengage the latch, the latch thereby disengaging from the contact carrier, causing the contact carrier to move from the first position to the second position. The GFCI circuit detects ground faults and deenergizes the solenoid when a ground fault is detected. The GFCI includes GFCI detection circuitry, wherein the GFCI detection circuitry includes an SCR switch for controlling energizing current for the solenoid; SCR Test Bias circuit for biasing the SCR switch; Self-Test Fault circuit for testing the operation of the GFCI detection circuitry; an Isolation circuit for isolating GFCI detection circuit while self-test is preformed; and power supply circuits for powering the GFCI circuit.

A testing module for a semiconductor wafer-form package includes a circuit board structure, first connectors, a first connecting structure, second connectors, third connectors and a first bridge connector. The circuit board structure includes two edge regions and a main region located therebetween. The first connectors are located over the edge regions and connected to the circuit board structure. The first connecting structure is located over and distant from the circuit board structure. The second connectors and third connectors are located over and connected to the first connecting structure, where the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region. The first bridge connector is electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors.

A GFCI latching apparatus and circuit is provided. The latching apparatus includes a solenoid; a solenoid plunger, wherein the solenoid plunger comprises a groove; a conical spring disposed at one end of the solenoid plunger; a forked latch, wherein the forked latch engages the groove with its forks. The latch also includes a bevel surface. Also included is a contact carrier having a first position when the solenoid is energized and a second position when the solenoid is deenergized. The contact carrier includes a bevel surface for mating with the latch bevel surface when the solenoid is energized. Also included is a GFCI configured to deenergize the solenoid upon the occurrence of a fault to disengage the latch, the latch thereby disengaging from the contact carrier, causing the contact carrier to move from the first position to the second position. The GFCI circuit detects ground faults and deenergizes the solenoid when a ground fault is detected. The GFCI includes GFCI detection circuitry, wherein the GFCI detection circuitry includes an SCR switch for controlling energizing current for the solenoid; SCR Test Bias circuit for biasing the SCR switch; Self-Test Fault circuit for testing the operation of the GFCI detection circuitry; an Isolation circuit for isolating GFCI detection circuit while self-test is preformed; and power supply circuits for powering the GFCI circuit.

A semiconductor die includes: a SiC substrate; power and current sense transistors integrated in the substrate such that the current sense transistor mirrors current flow in the main power transistor; a gate terminal electrically connected to gate electrodes of both transistors; a drain terminal electrically connected to a drain region in the substrate and which is common to both transistors; a source terminal electrically connected to source regions of the power transistor; a dual mode sense terminal; and a doped resistor region in the substrate between the transistors. The dual mode sense terminal is electrically connected to source regions of the current sense transistor. The doped resistor region has an opposite conductivity type as the source regions of both transistors and is configured as a temperature sense resistor that electrically connects the source terminal to the dual mode sense terminal.