A method of obtaining contact resistance values of a semiconductor package, the semiconductor package includes a package substrate, a semiconductor chip mounted on the package substrate, a molding member disposed on the package substrate to surround the semiconductor chip, and an electromagnetic interference (EMI) shielding layer disposed on side surfaces of the package substrate and on the molding member. The package substrate includes a substrate body having a first surface and a second surface which are opposite to each other, first to fourth upper interconnection patterns disposed on the first surface of the substrate body in a first region of the package substrate and in contact with the EMI shielding layer, and an interconnection structure disposed in a second region of the package substrate.

A method of obtaining contact resistance values of a semiconductor package, the semiconductor package includes a package substrate, a semiconductor chip mounted on the package substrate, a molding member disposed on the package substrate to surround the semiconductor chip, and an electromagnetic interference (EMI) shielding layer disposed on side surfaces of the package substrate and on the molding member. The package substrate includes a substrate body having a first surface and a second surface which are opposite to each other, first to fourth upper interconnection patterns disposed on the first surface of the substrate body in a first region of the package substrate and in contact with the EMI shielding layer, and an interconnection structure disposed in a second region of the package substrate.

An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.

An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.

A system for controlling power output of a power supply includes power conversion circuitry, output terminals, and a controller. The controller controls the power conversion circuitry to provide a known current to one or more leads, wherein the one or more leads are shorted at the distal end. The controller measures a voltage drop across the one or more leads shorted at the distal end. The controller stores a parameter determined based on the voltage drop, such as a resistance of the one or more leads. The controller controls the power conversion circuitry to provide a target voltage to the load based on the stored parameter when the one or more leads are not shorted at the load.

A system for controlling power output of a power supply includes power conversion circuitry, output terminals, and a controller. The controller controls the power conversion circuitry to provide a known current to one or more leads, wherein the one or more leads are shorted at the distal end. The controller measures a voltage drop across the one or more leads shorted at the distal end. The controller stores a parameter determined based on the voltage drop, such as a resistance of the one or more leads. The controller controls the power conversion circuitry to provide a target voltage to the load based on the stored parameter when the one or more leads are not shorted at the load.

An electrical equipment includes a first load configured for a nominal use of the equipment, at least one first metal screen, a sensor configured to measure a quantity characteristic of the first load, and a power supply conductor, wherein the first load and the at least first metal screen are linked electrically to the power supply conductor, and in that the equipment also comprises a comparator configured to compare measurements from the sensor to detect a dormant failure of the at least first metal screen.

A fault analysis method of a semiconductor fault analysis device is provided. The fault analysis method includes: receiving measurement data measured corresponding to a semiconductor device; generating double sampling data based on the measurement data and reference data; performing a fault analysis operation with respect to the double sampling data; classifying a fault type of the semiconductor device based on a result of the fault analysis operation; and outputting information about the fault type.

An electronic device including a processor and a sensor may be provided. The processor obtains a first degree of degradation of a first core based on a first parameter value associated with a lifetime of the first core and a first operating level associated with an operation of the first core. The processor obtains a second degree of degradation of a second core based on a second parameter value associated with a lifetime of the second core and a second operating level associated with an operation of the second core. The processor schedules a task of the first core and the second core based on the first degree of degradation and the second degree of degradation. The sensor provides the first parameter value and the first operating level to the first core and the second parameter value and the second operating level to the second core.

An electronic device including a processor and a sensor may be provided. The processor obtains a first degree of degradation of a first core based on a first parameter value associated with a lifetime of the first core and a first operating level associated with an operation of the first core. The processor obtains a second degree of degradation of a second core based on a second parameter value associated with a lifetime of the second core and a second operating level associated with an operation of the second core. The processor schedules a task of the first core and the second core based on the first degree of degradation and the second degree of degradation. The sensor provides the first parameter value and the first operating level to the first core and the second parameter value and the second operating level to the second core.