A test socket assembly which can stably transmit a signal at high communication speed comprises: a test socket having a plurality of conductive parts for electrically connecting a device terminal of the device to be tested and a board terminal of the tester board; a guide housing including a housing body having a housing opening into which the device to be tested can be inserted, and a socket supporting section disposed beneath the housing opening so as to protrude from one surface of the housing body; and a socket frame including a frame body, which is coupled to the test socket so as to be secured to the socket supporting section so that the test socket is supported beneath the housing opening, and a frame wing which is bent from the frame body toward the housing body so as to be secured to the housing body.

Techniques for usage metering by bias temperature instability with differential sensing on pairs of matching transistors are provided. In one aspect, a usage metering device includes: at least one metering circuit on a chip, the at least one metering circuit having a pair of matching transistors, and a differential current sense circuit connected to the pair of matching transistors, wherein the pair of matching transistors includes a reference transistor which is unused during regular operation of the chip, and a stressed transistor that is on continuously during the regular operation of the chip, and wherein the differential current sense circuit determines a Vt difference between the reference transistor and the stressed transistor. A method for usage metering and a method of forming a usage metering device are also provided.

A computing system may include a shadow feature model training engine configured to access a set of integrated circuit (IC) layouts and capacitance values determined for components of the set of IC layouts. The shadow feature model training engine may construct shadow feature training data for the set of IC layouts, including by extracting shadow features for components of the set of IC layouts, combine extracted shadow features and determined capacitance values to form the shadow feature training data, and may further train a machine-learning (ML) model with the shadow feature training data. The computing system may also include a shadow feature application engine configured to extract shadow features for components of an input IC layout and determine capacitance values for the input IC layout via the trained ML model.

An integrated circuit (IC) includes an input/output (IO) circuit in a first power domain, coupled between a first and second power supply terminal, and an integrity monitor in a second power domain, coupled between a third and fourth power supply terminal. The IO circuit includes an external terminal configured to communicate signals external to the IC, and an internal circuit node configured to provide a tap signal, wherein the internal circuit node is neither the first power supply terminal nor the second power supply terminal. The integrity monitor has a counter configured to provide a count value by counting each time the tap signal reaches a threshold voltage, and is configured to provide an integrity fault indicator based at least in part on the count value, in which the integrity fault indicator indicates whether or not a signal provided or received by the external terminal is trustworthy.

A voltage regulator circuit included in a computer system may generate a voltage level on a power supply signal using a source power supply signal and based initial values of one or more operation parameters derived from wafer-level test data. One or more operation characteristics of the voltage regulator circuit may be sampled, by a measurement circuit, at multiple time points to generated measurement data. A control circuit may adapt operation of the voltage regulator circuit based on the measurement data.

In a general aspect, a quantum error-correction technique includes applying a first set of two-qubit gates to qubits in a lattice cell, and applying a second, different set of two-qubit gates to the qubits in the lattice cell. The qubits in the lattice cell include data qubits and ancilla qubits, and the ancilla qubits reside between respective nearest-neighbor pairs of the data qubits. After the first and second sets of two-qubit gates have been applied, measurement outcomes of the ancilla qubits are obtained, and the parity of the measurement outcomes is determined.

A core partition circuit comprises a first decompression circuit, a second decompression circuit, a first switching circuit, an wrapper scanning circuit, a first compression circuit, a second compression circuit and a second switching circuit. The first and second decompression circuits decompress an input signal. The first switching circuit outputs the output signal of the first decompression circuit or the second decompression circuit according to a first control signal. The wrapper scanning circuit receives the output signal of the first decompression circuit or the second decompression circuit to scan the internal or the port of the core partition circuit. The first and second compression circuits respectively compress the internal logic and the port logic of the core partition circuit. The second switching circuit outputs the compressed internal logic or port logic of the core partition circuit according to the first control signal.

A temperature measurement member measures a temperature of an inspection object or a temperature of a mounting table on which the inspection object is placed inside an inspection apparatus that inspects the inspection object. The temperature measurement member is attached to an attachment position of a probe card used for electrical characteristic inspection in the inspection apparatus, and includes a main body having substantially a same shape as the probe card; a probe formed to extend from the main body toward the mounting table in a state in which the temperature measurement member is attached to the attachment position; and a temperature sensor configured to measure the temperature of the inspection object or the mounting table. The sensor transmits/receives a temperature measurement-related electrical signal to/from an inspection part via the probe card in the electrical characteristic inspection, and transmits a temperature measurement result to the inspection part.

A test circuit testing a storage circuit and including a controller, a pattern-generator circuit, a comparing circuit, and a first register is provided. The storage circuit includes a storage block. The controller is configured to generate a plurality of internal test signals. The pattern-generator circuit generates and provides test data to the storage circuit according to the internal test signal. The storage circuit writes the test data into the storage block and reads the storage block to generate read data. The comparing circuit compares the test data and the read data to generate a test result. The first register stores the test result. The controller determines whether the storage circuit is working normally according to the test result stored in the first register.

An integrated circuit for a semiconductor device that includes a first terminal for receiving a power supply voltage, a second terminal to which a load is to be coupled, and first and second metal-oxide-semiconductor (MOS) transistors each having a drain electrode and a source electrode, the source electrodes being respectively coupled to the first and second terminals. The integrated circuit includes a first line coupled to the drain electrode of the first MOS transistor and the drain electrode of the second MOS transistor, a second line to which a first voltage lower than the power supply voltage is applied, a first device configured to couple the first line and the second line, to prevent the first line from being brought into a floating state, and a detection circuit configured to detect a first abnormality in at least the first MOS transistor based on a voltage level of the first line.