A method, and forming an associated system, for testing semiconductor devices. Driver channels are provided, each driver channel connected to a storage device via a bus and connected to a respective semiconductor device. Each driver channel includes: a first voltage driver connected to the respective semiconductor device and having a first input for the respective semiconductor device, a second voltage driver connected to the respective semiconductor device and having a second input for the respective semiconductor device, first and second sets of optical switches in the first and second voltage driver respectively, and a microcontroller. All connections between the respective semiconductor device and both the first and second voltage drivers, in response to all optical switches of the first and second set of optical switches being closed. The semiconductor devices are tested, using the driver channels and the test parameters. The test results are provided to the storage device.

A method of testing semiconductor devices includes contacting bond pads coupled to integrated circuitry on a first die of a plurality of interconnected die on a substrate using a probe system having probes and probe tests including parametric tests, continuity tests, and a kill die subroutine. Probe tests using the probe program are performed. Die are binned into a first bin (Bin 1 die) for being a good die for all probe tests, or a second bin (Bin 2 die) for failing at least one of continuity tests and parametric tests. The Bin 2 die are divided into a first sub-group that failed the continuity tests and a second sub-group that do not fail the continuity tests. A kill die subroutine is triggered including applying power sufficient to selectively cause damage to the second sub-group of Bin 2 die to generate a continuity failure and thus generate kill die.

The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.

A method for increasing the reliability of transducers, having a first and a second IC, the two ICs have exactly the same or substantially the same monolithically integrated circuit components, each with a sensor and a signal contact designed for bidirectional data transmission and a reference contact and a supply voltage contact. A signal generated as a function of the physical quantity sensed by the relevant sensor is applied to the signal contact. The signal of the first IC is compared with the signal of the second IC by a monitoring device, and then the result of the comparison is communicated to an enable device, and the signal of the first IC is sent by an enable device to the control unit if both signals lie in a predefined useful band.

A method of making a secure integrated-circuit system comprises providing a first integrated circuit in a first die having a first die size and providing a second integrated circuit in a second die. The second die size is smaller than the first die size. The second die is transfer printed onto the first die and connected to the first integrated circuit, forming a compound die. The compound die is packaged. The second integrated circuit is operable to monitor the operation of the first integrated circuit and provides a monitor signal responsive to the operation of the first integrated circuit. The first integrated circuit can be constructed in an insecure facility and the second integrated circuit can be constructed in a secure facility.

An integrated circuit (IC) includes an input/output (IO) circuit in a first power domain, coupled between a first and second power supply terminal, and an integrity monitor in a second power domain, coupled between a third and fourth power supply terminal. The IO circuit includes an external terminal configured to communicate signals external to the IC, and an internal circuit node configured to provide a tap signal, wherein the internal circuit node is neither the first power supply terminal nor the second power supply terminal. The integrity monitor has a counter configured to provide a count value by counting each time the tap signal reaches a threshold voltage, and is configured to provide an integrity fault indicator based at least in part on the count value, in which the integrity fault indicator indicates whether or not a signal provided or received by the external terminal is trustworthy.

A semiconductor device includes a leadframe having a first level and a second level. The semiconductor device includes a semiconductor die and a conductive alloy. The conductive alloy is between the semiconductor die and the first level of the lead frame. The conductive alloy is configured to be a current sense element. The semiconductor device further includes a first conductive post coupling the semiconductor die to the conductive alloy, a second conductive post coupling the semiconductor die to the conductive alloy, and a third conductive post coupling the semiconductor die to the second level of the lead frame. The second conductive post is configured to be a first sense terminal. The third conductive post is configured to be a second sense terminal.

An integrated circuit (IC) includes subcircuits, power switches coupled to pass load current to a respective one of the subcircuits when activated by a respective switch control signal, and sensing circuits. Each of the sensing circuits is coupled to a respective one of the subcircuits, wherein the sensing circuits are configured to generate sense currents that are proportional to the respective load currents. The IC also includes a conversion circuit configured to receive at least one of the sense currents and to convert the at least one of the sense currents to an equivalent multi-bit digital signal, a timestamp circuit configured to generate a timestamp value that is correlated with the multi-bit digital signal, and a controller configured to provide signals to operate the power switches and the sensing circuits.

In some examples, a device includes a control circuit configured to deliver driving signals to a switch. The device also includes a testing circuit configured to cause the control circuit to toggle the switch at a first instance and determine a parameter magnitude at the switch at a second instance after toggling the switch at the first instance by at least determining a voltage magnitude at the switch at the second instance. The testing circuit is also configured to cause the control circuit to toggle the switch after the second instance and determine a parameter magnitude at the switch at a third instance after toggling the switch after the second instance. The testing circuit is further configured to generate an output based on the determined parameter magnitudes at the switch at the second and third instances.

An integrated circuit includes a plurality of power transistor driver channels for driving external loads. The driver channels can be selectively configured as high side or low side driver channels. The integrated circuit includes, for each driver channel, a respective analog test circuit and a respective controller. The integrated circuit includes a single counter connected to each of the controllers for simultaneously controlling off-state diagnosis timing windows for the driver channels.