A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.

The present invention provides a semiconductor integrated circuit for detecting leakage current to determine whether an electric leakage occurs in an electric line based on an induced voltage input from a leakage current detection unit 20 installed in the electric line, and an earth, leakage circuit breaker having the semiconductor integrated circuit. A semiconductor integrated circuit 100 for detecting leakage current includes: a signal amplification unit 110 configured to amplify the induced voltage; an interruption determination unit 130 configured to compare an output voltage output from the signal amplification unit with a preset reference voltage, and output an interruption signal for interrupting a power supply to the electric line; a flare current stabilization (FCS) circuit 150 for a signal amplification unit connected to the signal amplification unit; and a flare current stabilization (FCS) circuit 170 for an interruption determination unit connected to the interruption determination unit.

An input/output (I/O) sensor for a multi-IC module. The I/O sensor includes: delay circuitry, configured to receive a data signal from an interconnected part of an IC of the multi-IC module and to generate a delayed data signal, the delay circuitry including an adjustable delay-line configured to delay an input signal by a set time duration; a comparison circuit, configured to generate a comparison signal by comparing the data signal with the delayed data signal; and processing logic, configured to set the time duration of the adjustable delay-line and, based on the comparison signal, identify a margin measurement of the data signal for determining an interconnect quality parameter.

An input/output (I/O) sensor for a multi-IC module. The I/O sensor includes: delay circuitry, configured to receive a data signal from an interconnected part of an IC of the multi-IC module and to generate a delayed data signal, the delay circuitry including an adjustable delay-line configured to delay an input signal by a set time duration; a comparison circuit, configured to generate a comparison signal by comparing the data signal with the delayed data signal; and processing logic, configured to set the time duration of the adjustable delay-line and, based on the comparison signal, identify a margin measurement of the data signal for determining an interconnect quality parameter.

In an embodiment, a method includes filtering, with a low-pass filter, a voltage signal (V.sub.dd) of a chip to create a filtered signal (V.sub.ref). The method further includes dividing V.sub.ref by a given factor. The method further includes determining whether a voltage droop occurred in V.sub.dd by comparing V.sub.dd to the divided V.sub.ref. The method further includes outputting a droop detection signal if V.sub.dd is less than the divided V.sub.ref. In an embodiment, dividing V.sub.ref by the given factor includes selecting, with a multiplexer, one of a plurality of divided V.sub.ref signals outputted by a voltage divider. The selecting is based on a selection signal.

This document describes techniques and systems for leakage screening based on power prediction. In particular, the described systems and techniques estimate, during a silicon manufacturing process, use-case power (e.g., low power, ambient power, high power, gaming power) to apply leakage screening for apart (e.g., a chip package). In some aspects, measurable silicon parameters (e.g., leakage values, bin values, processor sensor values) may be used for use-case power prediction. Using the described techniques, a maximum allowable predicted use-case power can be determined and used for leakage screening regardless of an individual rail leakage or voltage bin assignment.

A system for data creation, storage, analysis, and training while margin testing includes a margin test generator coupled through an interface to a Device Under Test (DUT). The margin test generator is structured to modify test signals for testing the DUT during one or more testing states of a test session to create testing results. The testing results are stored in a data repository along with a DUT identifier of the DUT tested during the test session. A comparator determine whether any results of the DUT test results match a predictive outcome that is based from an analysis of previous DUT tests. If so, a message generator produces an indication that the tested DUT matched the predictive outcome.

The present disclosure relates to an adaptive body biasing or voltage regulation circuit for a circuit region, comprising: a first delay module configured to delay a local clock signal to generate first and second output signals delayed by first and second delays; a multiplexer configured to select one of the first and second output signals; a first slack monitor circuit configured to generate a first detection signal indicating when a slack time of the first and second output signals is less than a first threshold; a voltage generation circuit configured to generate a supply voltage for the circuit region, or at least one biasing voltage for biasing wells of transistors in the circuit region, using a further control loop comprising a process, voltage and/or temperature sensor; and a control circuit configured to adjust a gain of the further control loop based on the first detection signal.

A margin tester including an identification reader configured to receive an adaptor identifier of an adaptor, an interface configured to connect to a device under test through the adaptor, and one or more processors configured to assess a margin, such as an electrical margin or an optical margin, of a device under test and tag the assessment with the adaptor identifier. Assessing the margin can include assessing the margin based on an expected margin that is predicted or provided based on the adaptor identifier.

A testing device includes a measuring unit, a testing board supporting the measuring unit and connected to the measuring unit, and a connecting interface coupled to the testing board. The connecting interface includes connecting terminals protruding in a direction away from the testing board, and is connected to a device under test (DUT) via the connecting terminals. When the DUT is connected to the connecting interface, the measuring unit supplies a constant electric current via the testing board and the connecting interface to the DUT for a preset duration to result in a voltage, measures the voltage, and determines, based on a result of measurement of the voltage, an electrical connection status of the DUT.