The present disclosure provides methods for testing and evaluating electrical parameters of electronic circuits. An exemplary method includes providing a device-under-test electrically coupled to a testing apparatus; and determining an optimum value of a first electrical parameter and an optimum value of a second parameter by testing the device-under-test according to a set of first electrical parameter values and a set of second electrical parameter values. The optimum value of the first electrical parameter and the optimum value of the second parameter are determined based on an electrical noise response of the device-under-test.

The performance of a microelectronic circuit can be configured by making an operating parameter assume an operating parameter value. An operating method comprises selectively setting the microelectronic circuit into a test mode that differs from a normal operating mode of the microelectronic circuit, and utilizing said test mode to input test input signals consisting of test input values into one or more adaptive processing paths within the microelectronic circuit. An adaptive processing path comprises processing logic and register circuits configured to produce output values from input values input to them. The performance of such an adaptive processing path can be configured by making an operating parameter assume an operating parameter value. The method comprises making said one or more adaptive processing paths form test output values on the basis of the respective test input values input to them, and forming a set of test output signals by collecting said test output values given by said one or more adaptive processing paths. The method comprises examining said set of test output signals, and forming a test result on the basis of said examining, and using said test result to select and set an operating parameter value for said operating parameter.

An isolated differential current shunt measurement probe for a test and measurement system having an isolation barrier between an input side and output side of the probe. The input side is configured to receive a voltage signal across a current shunt connected to a device under test and transmit the voltage signal across the isolation barrier. The output side is configured to receive the voltage signal across the isolation barrier and output the voltage signal to a test and measurement instrument.

An apparatus for detecting a wiring short in a substrate includes a voltage source configured to apply a rising or falling measurement voltage to a first wiring of a substrate, a plurality of electrodes including first and second electrode elements capacitively coupled to the first and second wirings of the substrate, respectively, a sensing circuit configured to generate an output voltage based on a voltage or a current between the first and second electrode elements, and a processor configured to determine whether a short circuit connection having a resistance value greater than a reference resistance value is present between the first and second wirings based on a change rate of the output voltage after application of the measurement voltage. Methods for detecting wiring shorts in the substrate are further provided.

Systems, methods, and apparatuses are described for verifying the authenticity of an integrated circuit device. An integrated test apparatus may use quiescent current and/or conducted electromagnetic interference readings to determine if a device under test matches the characteristics of an authenticated device. Deviations from the characteristics of the authenticated device may be indicative of a counterfeit device.

A computer system may determine a first set of output values for a set of test paths at a first time. Each output value may correspond to a test path in the set of test paths. The computer system may then determine a second set of output values at a second time. Each output value in the second set of output values may have an associated output value in the first set of output values. The computer system may then determine whether degradation of the semiconductor chip has occurred by comparing the first set of output values to the second set of output values.

This disclosure generally relates to repeaters, and, in particular, repeaters for open-drain systems. In one embodiment, an apparatus comprises a first port, a second port, a current detector, a transistor, and a control logic circuit. A current detector input of the current detector is coupled to the first port. A transistor channel electrode of the transistor is coupled to the second port. A control logic circuit input of the control logic circuit is coupled to the current detector output, and a control logic circuit output of the control logic circuit is coupled to a transistor control electrode of the transistor.

An image-capturing unit includes: an image-capturing chip; a power supply circuit unit that outputs electrical power to be fed to the image-capturing chip; a power supply line that feeds electrical power from the power supply circuit unit to the image-capturing chip; a disconnecting unit that is provided to the power supply line and is electrically disconnecting the power supply circuit unit and the image-capturing chip when a leakage current of the image-capturing chip is measured; and an implementation substrate on which the power supply circuit unit, the image-capturing chip, the power supply line and the disconnecting unit are implemented.

A method for characterizing an integrated circuit that selecting at least two devices from an integrated circuit for measuring light emission, wherein each of the at least two devices have experienced a different level of stress, applying power to the integrated circuit, and measuring the light emission from the at least two devices. The method also includes comparing the light emission that is measured from the at least two devices, wherein a difference between the light emission that is measured from the at least two devices greater than a predetermined ratio indicates that at least one of the devices from the at least two devices has a below specification performance.

A method for detecting error on an input/output (IO) pin of an integrated circuit includes using the input/output pin of the integrated circuit in a first mode by receiving or sending a first value as analog data or digital data. The input/output pin is toggled in a test mode after each instance of using the input/output pin in the first mode. The test mode includes providing a second value disparate from the first value during a set time after using the input/output pin in the first mode, receiving back during the set time a resulting value based on providing the second value, measuring the resulting value, and identifying an error on the input/output pin of the integrated circuit based on the measured resulting value.