A random pulse generator includes: a randomness test circuit suitable for testing randomness of a random pulse; a control circuit suitable for generating frequency control information and puke control information based on a test result of the randomness test circuit; a periodic wave generating circuit suitable for generating a periodic wave whose frequency is changed based on the frequency control information; and a pulse generating circuit suitable for generating the random pulse based on the periodic wave and the pulse control information.

It is described a leakage compensation circuit for a measurement device which comprises a measurement circuit with a leaking device that is connected to a measurement path and causes a leakage current. The leakage compensation circuit comprises: i) a replica device of the leaking device, wherein the replica device is connected to a replica path, and wherein the replica device is configured to cause a replica leakage current that is essentially equal to the leakage current of the leaking device, ii) a voltage regulator which is connected to the measurement path and to the replica path, wherein the voltage regulator is configured to regulate the voltage in the replica path based on the voltage of the measurement path, and iii) a current mirror which is connected to the measurement path and to the replica path, wherein the current mirror is configured to mirror the replica leakage current of the replica device into the measurement path.

A failure positioning method for positioning leakage defect cell between the gate and the active region of transistor cells arranged in an array. The positioning method includes the steps of: measuring the resistance between a first metal wire connecting the active regions and a second metal wire connecting the gates, and positioning a first region where the defect cell is located by resistance ratio; electrically isolating the active region contact holes and the gate contact holes from each other; shorting the gate contact holes in the first region; and performing active voltage contrast analysis on the plurality of columns of transistor cells in the first region to position the leakage defect in the first region by comparing the voltage contrast images. With the positioning method, the transistor cell having a leakage defect at nA level may be accurately found from a plurality of transistor cells arranged in an array. The positioning method helps to improve the yield of semiconductor device based on the above defect adjustment process.

An object of the present invention is to provide a technique of duplexing monitor circuits in which a common cause failure can be eliminated. A semiconductor device has: a first monitor circuit monitoring that temperature or voltage of the semiconductor device is within a normal operation range; and a second monitor circuit monitoring normal operation of the first monitor circuit. The first and second monitor circuits generate information of temperature or voltage on the basis of different principles.

A method of determining a phase misalignment between a first signal generated from a first signal path and a second signal generated from a second signal path may include obtaining multiple samples of the first signal proximate to when the first signal crosses zero wherein the first signal can be approximated as linear; obtaining multiple samples of the second signal proximate to when the second signal crosses zero wherein the first signal can be approximated as linear; based on the multiple samples of the first signal, approximating a first time at which the first signal crosses zero; based on the multiple samples of the second signal, approximating a second time at which the second signal crosses zero; and determining the phase misalignment between the first signal and the second signal based on a difference between the first time and the second time.

A mounting structure minimizes the influence of displacements, along a length direction of a resistor, in mounting positions of capacitor electrodes on the electrical characteristics of a circuit including a parallel circuit composed of a capacitor and the resistor. The capacitor has first and second electrodes, which respectively include first and second side surface portions disposed in parallel to a length direction of the resistor. The resistor has a first resistance body corresponding to the first side surface portions and a second resistance body corresponding to the second side surface portions that are separately disposed along the length direction and connected in series via a wire, and is mounted so that the first resistance body is positioned directly facing the first side surface portions and the second resistance body is positioned directly facing the second side surface portions.

A performance testing method for determining a performance of a device under test having non-linear characteristics is disclosed. The performance testing method comprises the following steps: generating a hard clipper model of said device under test; generating a test signal having predefined properties; forwarding said test signal to the device under test, wherein the device under test generates an output signal based on said test signal; feeding said hard clipper model with said test signal, thereby generating a model output signal; and comparing said output signal to said model output signal in order to determine the performance of the device under test. Moreover, a measurement system for determining a performance of a device under test having non-linear characteristics is disclosed.

A temperature measurement circuit includes a band-gap reference circuit configured to generate a band-gap reference voltage that is fixed regardless of an operation temperature, a reference voltage generator circuit configured to generate a measurement reference voltage by adjusting the band-gap reference voltage, a sensing circuit configured to generate a temperature-variant voltage based on a bias current, where the temperature-variant voltage is varied depending on the operation temperature, an analog-digital converter circuit configured to generate a first digital code indicating the operation temperature based on the measurement reference voltage and the temperature-variant voltage, and an analog built-in self-test (BIST) circuit configured to generate a plurality of flag signals indicating whether each of the band-gap reference voltage, the measurement reference voltage, and a bias voltage corresponding to the bias current is included in a predetermined range.

A system may include a trim circuit configured to provide a trim signal to a circuit under test. The trim circuit may be configured to adjust a trim value of the trim signal based on a selection signal and a value signal. The trim signal may cause a key characteristic of the circuit under test to change based on the adjusted trim value. The system may include a production tester configured to determine whether the key characteristic is within a threshold range. Responsive to the key characteristic being within the threshold range, the production tester may stop performing the trim procedure on the circuit under test. Responsive to the key characteristic not being within the threshold range, the production tester may adjust the value signal based on whether the key characteristic is greater than or less than the threshold range.

A method for estimating jitter of a clock signal includes generating a phase-adjusted clock signal based on an input clock signal and a feedback clock signal using a frequency-divided clock signal. The method generating N digital time codes for each phase adjustment of P phase adjustments of the phase-adjusted clock signal using a reference clock signal. Each digital time code of the N digital time codes corresponds to a first edge of a clock signal based on the frequency-divided clock signal. P is a first integer greater than zero and N is a second integer greater than zero. The method includes generating a jitter indicator based on an expected period of the clock signal and the N digital time codes for each phase adjustment of the P phase adjustments.