A solid state drive (SSD) with improved techniques for testing power loss protection (PLP) capacitors and a method for testing PLP capacitors of SSDs is disclosed. In one embodiment, the SSD includes a memory controller and one or more non-volatile memory devices and a volatile memory device coupled to the memory controller. The SSD also includes a PLP capacitor configured to supply a first voltage to the memory controller, the one or more non-volatile memory devices, and the volatile memory device in the event of a power loss or failure of the SSD. In one embodiment, the PLP capacitor is further configured to increase the first voltage to a second voltage prior to testing the PLP capacitor. In another embodiment, the memory controller is configured to reduce a volume of data stored in the volatile memory device prior to testing the PLP capacitor.

A method and a device for measuring a plurality of semiconductor chips in a wafer array are disclosed. In an embodiment a method for measuring the semiconductor chips in a wafer array, wherein the wafer array is arranged on an electrically conductive carrier so that in each case back contacts of the semiconductor chips are contacted by the carrier, wherein a contact structure is arranged on a side of the wafer array facing away from the carrier, and wherein the contact structure includes a contact element and/or a plurality of radiation-emitting measurement semiconductor chips, includes applying a voltage between the contact structure and the carrier and measuring the semiconductor chips depending on a luminous image which is generated by emitted radiation which is caused simultaneously by fluorescence when the semiconductor chips are illuminated or by a radiation-emitting operation of the measurement semiconductor chips when the voltage is applied.

The present invention provides a chip comprising a circuit module, a power switch and a detection and control circuit. The power switch is coupled between a supply voltage and the circuit module, and is used to selectively connect the supply voltage to the circuit module, and control a current amount flowing into the circuit module according to at least a control signal. The detection and control circuit is coupled to the power switch, and is used to detect a first signal generated by a first circuit positioned surrounding the circuit module, and compare the first signal with a second signal in a real-time manner to generate the control signal to adjust the current amount flowing into the circuit module.

A circuit test method for a test device to test a device under test is provided. The circuit test method includes the steps of applying zero volts to a plurality of power pins of the device under test; applying a test voltage to a first signal pin among a plurality of signal pins of the device under test; and measuring a current on a second signal pin among the plurality of signal pins of the device under test and determining whether there is a leakage current in the device under test.

A wireless test system includes a load board having an upper surface and a lower surface. The load board has a testing antenna disposed on the load board. A socket for receiving a device under test (DUT) having an antenna structure therein is disposed on the upper surface of the load board. The antenna structure is aligned with the testing antenna. The wireless test system further includes a handler for picking up and delivering the DUT to the socket. The handler has a clamp for holding and pressing the DUT. The clamp is grounded during testing and functions as a ground reflector that reflects and reverses radiation pattern of the DUT from an upward direction to a downward direction toward the testing antenna.

A method for testing system-on-a-chip (SoC) for faults at subthreshold or substantially at threshold operating voltages includes the steps of testing the SoC for fault at a favorable operating voltage, the testing including measuring a metric characterizing the fault at the favorable operating voltage to obtain a first metric value; and retesting the SoC for the fault at a first operating voltage upon the first metric value at the favorable operating voltage being correlated, according to a metric correlation establishing a correlation relationship between the favorable operating voltage and the first operating voltage, to a second metric value at the first operating voltage within a predictive interval of the metric correlation.

A method for testing system-on-a-chip (SoC) for faults at subthreshold or substantially at threshold operating voltages includes the steps of testing the SoC for fault at a favorable operating voltage, the testing including measuring a metric characterizing the fault at the favorable operating voltage to obtain a first metric value; and retesting the SoC for the fault at a first operating voltage upon the first metric value at the favorable operating voltage being correlated, according to a metric correlation establishing a correlation relationship between the favorable operating voltage and the first operating voltage, to a second metric value at the first operating voltage within a predictive interval of the metric correlation.

A first score and a second score for each scan cell are first determined based on numbers of test cubes in a set of test cubes having a specified value of 1 and a specified value of 0 for the each scan cell, respectively. A ranking score for each test cube in the set of test cubes is then determined based on combining the first scores and the second scores corresponding to specified bits of the each test cube in the set of test cubes. Test cubes in the set of test cubes are merged according to a sequence based on the ranking scores in a test pattern generation process.

A source driver includes a first output pad, a second output pad, a first charge-sharing path, a second charge-sharing path, a first charge-sharing switch, a second charge-sharing switch and a test circuit. A first terminal and a second terminal of the first charge-sharing switch are respectively coupled to the first output pad and the first charge-sharing path. A first terminal and a second terminal of the second charge-sharing switch are respectively coupled to the second output pad and the second charge-sharing path. The test circuit is coupled to the first charge-sharing path and the second charge-sharing path. The test circuit performs a test for the first output pad and the second output pad via the first charge-sharing path, the second charge-sharing path, the first charge-sharing switch and the second charge-sharing switch in a test period.

The present invention provides a semiconductor integrated circuit for detecting leakage current to determine whether an electric leakage occurs in an electric line based on an induced voltage input from a leakage current detection unit 20 installed in the electric line, and an earth, leakage circuit breaker having the semiconductor integrated circuit. A semiconductor integrated circuit 100 for detecting leakage current includes: a signal amplification unit 110 configured to amplify the induced voltage; an interruption determination unit 130 configured to compare an output voltage output from the signal amplification unit with a preset reference voltage, and output an interruption signal for interrupting a power supply to the electric line; a flare current stabilization (FCS) circuit 150 for a signal amplification unit connected to the signal amplification unit; and a flare current stabilization (FCS) circuit 170 for an interruption determination unit connected to the interruption determination unit.