A testing device includes a testing socket and a reflector. The testing socket defines an accommodating space. The reflector is disposed in the accommodating space and has a plurality of reflection surfaces non-parallel with each other. The reflection surfaces define a transmission space.

A capacitive intelligent workstation detection system, comprising a capacitance detection sensor (1), a capacitive sensing module (201), a microprocessor module (202), a remote management platform (3) and a mobile APP, the capacitance detection sensor (1) detecting a capacitance change when a human body approaches, and after being processed by the capacitive sensing module (201), the capacitance change being sent to the microprocessor module (202) to form workstation state data, the workstation state data being sent to the remote management platform (3), and the remote management platform (3) processing the workstation state data, so as to obtain user habit data. A user uses the mobile APP to obtain relevant data by means of the remote management platform (3), and sends debugging and control information to a workstation detection device (2). The system uses the capacitive sensing module (201), has a small volume, a good concealment, a beautiful appearance and a flexible design, does not require complex optical and microwave devices and has no mechanical device, is less vulnerable to aging and abrasion, and has a long service life and good consistency. The remote management platform (3) serves as a data management and control center, and the mobile APP provides man-machine bidirectional interaction, so as to implement office electric appliance linkage energy-saving management and personnel management.

Methods of characterizing electrical properties of a semiconductor layer structure on a wafer with topside semiconductor layers on an insulating or semi-insulating substrate, the semiconductor layer structure including a high electron mobility transistor (HEMT) heterostructure with a two-dimensional electron gas (2DEG) at a heterointerface between the semiconductor layers of the heterostructure. The methods include: (a) physically contacting the topside of the wafer within a narrow border zone at an edge of the wafer with a flexible metal cantilever electrode of a contacting device, wherein the flexible metal cantilever electrode contacts one or more of the semiconductor layers exposed at the narrow border zone so that the flexible metal cantilever electrode is in electrical contact with the 2DEG; and (b) applying corona charge bias and measuring a surface voltage of the semiconductor layers using a non-contact probe while maintaining the electrical contact with the 2DEG. The physical contacting to the topside of the wafer is noncontaminating and noninvasive to the semiconductor layers.

An inspection device includes a reference signal output section, a noise removal section, and an electrical characteristic measurement section. The reference signal output section is connected to an external power supply device in electrical parallel with a semiconductor sample, and outputs a reference signal according to the output of the external power supply device. The noise removal section outputs a noise removal signal obtained by removing a noise component of the output of the external power supply device from the current signal output from the semiconductor sample based on the reference signal. The electrical characteristic measurement section measures the electrical characteristic of the semiconductor sample based on the noise removal signal. The inspection device measures the electrical characteristic of the semiconductor sample to which a voltage is being applied by the external power supply device and which is being irradiated and scanned with light. The inspection device outputs a defective portion of the semiconductor sample based on the electrical characteristic.

Methods, systems and techniques are provided to authenticate a device under test (DUT)/system under test (SUT) comprising an electronic component(s). A profile is defined by injecting a signal to elicit an output that is responsive a physical characteristic of the type of DUT/SUT. In respective embodiments the injected signal is defined to elicit an output for time-domain or frequency-domain evaluation. An injected signal may comprise combinations of (non-destructive/non-activating) signals applied to multiple access points for measurement at arbitrary access points of the DUT/SUT. In an embodiment, measurements of multiple DUT/SUTs of a same type are used to define a common profile. In an embodiment, the profile is built using machine learning to define a classifier. In other embodiments, statistical profiles are defined. During use, output is generated for a target DUT/SUT for evaluation relative to the profile. Counterfeit/alternate designs, altered designs, and implants are detectable.

The present disclosure describes exemplary methods and systems that are applicable for hardware authentication, counterfeit detection, and in-field tamper detection in both printed circuit board and/or integrated circuit levels by utilizing random variations in boundary-scan path delay and/or current in the industry-standard JTAG-based design-for-test structure to generate unique device identifiers.

System and method for compensating for power loss due to a radio frequency (RF) signal probe mismatch in conductive RF signal testing of a RF data signal transceiver device under test (DUT). Sourcing the RF test signal with the RF vector signal transceiver at multiple test frequencies enables isolation of and compensation for power loss due to a mismatch between the RF signal probe and RF DUT connection based on predetermined losses of the RF signal path.

The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

The present invention discloses an in-situ monitoring method and apparatus for a power electronic device explosion. A power electronic device is excited to produce an explosion failure by using a fault excitation module. An electrical signal of the power electronic device is monitored in real time by using an electrical signal monitoring module. Gas information of a test cavity is monitored in real time by using a gas monitoring module. External pictures of the power electronic device are captured by using a high-speed image capturing module. Internal pictures of the power electronic device are captured by using a high-speed X-ray imaging module. Each module in the apparatus is triggered to work according to a predetermined time sequence and time interval by using a time sequence control module. The entire apparatus is controlled and data is acquired, stored, and displayed by using a main control module.

The present invention discloses an in-situ monitoring method and apparatus for a power electronic device explosion. A power electronic device is excited to produce an explosion failure by using a fault excitation module. An electrical signal of the power electronic device is monitored in real time by using an electrical signal monitoring module. Gas information of a test cavity is monitored in real time by using a gas monitoring module. External pictures of the power electronic device are captured by using a high-speed image capturing module. Internal pictures of the power electronic device are captured by using a high-speed X-ray imaging module. Each module in the apparatus is triggered to work according to a predetermined time sequence and time interval by using a time sequence control module. The entire apparatus is controlled and data is acquired, stored, and displayed by using a main control module.