A measuring system has an analog-to-digital converter, an acquisition memory, a processing unit, and a display memory. The processing unit is adapted to decode a digital signal according to a protocol creating a decoded signal and to evaluate the decoded signal at a cursor position. The digital data generated by decoding the decoded signal at the cursor position is stored in the display memory. Further, a method for analyzing an analog signal according to a protocol is shown.

An apparatus includes a linear analog circuit and data-check circuit. The linear analog circuit receives analog input signals and provides processed analog output signals. The linear analog circuit includes voltage-changing and voltage-impedance circuitry that perform processing of the analog input signals by the linear analog circuit and an analog test bus circuit (ATB) that selectively passes different ones of a plurality of input ports to at least one output port. A data-check circuit is communicatively coupled to the ATB and includes a data-processing circuit that detects an error conveyed by the linear analog circuit by applying a control signal, while the linear analog circuit and the data-check circuit facilitate testing of the linear analog circuit, to cause the ATB to selectively pass the different ones of the plurality of input ports.

An apparatus includes a linear analog circuit and data-check circuit. The linear analog circuit receives analog input signals and provides processed analog output signals. The linear analog circuit includes voltage-changing and voltage-impedance circuitry that perform processing of the analog input signals by the linear analog circuit and an analog test bus circuit (ATB) that selectively passes different ones of a plurality of input ports to at least one output port. A data-check circuit is communicatively coupled to the ATB and includes a data-processing circuit that detects an error conveyed by the linear analog circuit by applying a control signal, while the linear analog circuit and the data-check circuit facilitate testing of the linear analog circuit, to cause the ATB to selectively pass the different ones of the plurality of input ports.

To provide a semiconductor device capable of easily testing a built-in self-test control circuit itself, the semiconductor device has: a test pattern generator; an output response analyzer configured to compare an expected value to a test result of a circuit; a plurality of test control circuits each configured to control the test pattern generator and the output response analyzer; and a circuit under test. The semiconductor device has: a first test mode in which a first test control circuit controls the test pattern generator and the output response analyzer to cause the test pattern, to thereby perform a test; and a second test mode in which the test control circuit other than the first test control circuit controls the test pattern generator and the output response analyzer to cause the test pattern, to thereby perform a test.

To provide a semiconductor device capable of easily testing a built-in self-test control circuit itself, the semiconductor device has: a test pattern generator; an output response analyzer configured to compare an expected value to a test result of a circuit; a plurality of test control circuits each configured to control the test pattern generator and the output response analyzer; and a circuit under test. The semiconductor device has: a first test mode in which a first test control circuit controls the test pattern generator and the output response analyzer to cause the test pattern, to thereby perform a test; and a second test mode in which the test control circuit other than the first test control circuit controls the test pattern generator and the output response analyzer to cause the test pattern, to thereby perform a test.

An analog circuit fault diagnosis method using a single testable node comprises the following steps: (1) obtaining prior sample data vectors under each fault mode; (2) computing a statistical average of the prior sample data vectors under each of the fault modes; (3) decomposing a signal by an orthogonal Haar wavelet filter set; (4) extracting the feature factor of the prior sample fault modes; (5) extracting a fault-mode-to-be-tested feature factor; (6) computing a correlation coefficient matrix and correlation metric parameters between the feature factor of the prior sample fault modes and the feature factor of the fault-mode-to-be-tested; and (7) determining a fault mode according to a maximal correlation principle by comparing the correlation metric parameters. The method can convert a single signal into a plurality of signals without losing original measurement information, and extract an independent fault mode feature factor reflecting variations of a circuit structure in different fault modes, can be used to study an associated mode determination rule and successfully complete classification of circuit fault modes.

An analog circuit fault diagnosis method using a single testable node comprises the following steps: (1) obtaining prior sample data vectors under each fault mode; (2) computing a statistical average of the prior sample data vectors under each of the fault modes; (3) decomposing a signal by an orthogonal Haar wavelet filter set; (4) extracting the feature factor of the prior sample fault modes; (5) extracting a fault-mode-to-be-tested feature factor; (6) computing a correlation coefficient matrix and correlation metric parameters between the feature factor of the prior sample fault modes and the feature factor of the fault-mode-to-be-tested; and (7) determining a fault mode according to a maximal correlation principle by comparing the correlation metric parameters. The method can convert a single signal into a plurality of signals without losing original measurement information, and extract an independent fault mode feature factor reflecting variations of a circuit structure in different fault modes, can be used to study an associated mode determination rule and successfully complete classification of circuit fault modes.

Embodiments herein relate to apparatus, systems, and methods to compress a test pattern onto a field programmable gate array to test a device under test. This may include identifying values of a plurality of drive pins for a plurality of test cycles to apply to an input of the DUT for each of the plurality of test cycles, identifying values of a plurality of compare pins for the plurality of test cycles to compare an output of the DUT, respectively, for each of the plurality of test cycles, analyzing the identified values, compressing, based on the analysis, the values of the plurality of drive pins and the plurality of compare pins, and storing the compressed values on the FPGA.

An analog circuit fault feature extraction method based on a parameter random distribution neighbor embedding winner-take-all method, comprising the following steps: (1) collecting a time-domain response signal of an analog circuit under test, wherein the input of the analog circuit under test is excited by using a pulse signal, a voltage signal is sampled at an output end, and the collected time-domain response signal is an output voltage signal of the analog circuit; (2) applying a discrete wavelet packet transform for the collected time-domain response signal to acquire each wavelet node signal; (3) calculating energy values and kurtosis values of the acquired wavelet node signals to form an initial fault feature data set of the analog circuit; and (4) analyzing the initial fault feature data by the parameter random distribution neighbor embedding winner-take-all method, to acquire optimum low-dimensional feature data. The invention effectively reduces redundancy and interference elements in the fault features, and greatly improves degree of separation of different fault features and degree of polymerization of samples of same fault category.

An analog circuit fault feature extraction method based on a parameter random distribution neighbor embedding winner-take-all method, comprising the following steps: (1) collecting a time-domain response signal of an analog circuit under test, wherein the input of the analog circuit under test is excited by using a pulse signal, a voltage signal is sampled at an output end, and the collected time-domain response signal is an output voltage signal of the analog circuit; (2) applying a discrete wavelet packet transform for the collected time-domain response signal to acquire each wavelet node signal; (3) calculating energy values and kurtosis values of the acquired wavelet node signals to form an initial fault feature data set of the analog circuit; and (4) analyzing the initial fault feature data by the parameter random distribution neighbor embedding winner-take-all method, to acquire optimum low-dimensional feature data. The invention effectively reduces redundancy and interference elements in the fault features, and greatly improves degree of separation of different fault features and degree of polymerization of samples of same fault category.