A method for determining relevance values representing a relevance of a combination of an input node of a first number of input nodes with a measurement node of a second number of measurement nodes for a detection of a fault on a chip applies a third number of tests at the first number of input nodes, measures for each test of the third plurality of tests a signal at each of the second number of measurement nodes to obtain for each measurement node of the second number of measurement nodes a third number of measurement values, and determines the relevance values, wherein each relevance value is calculated based on a correlation between the third number of test input choices defined for the input node of the respective combination and the third number of measurement values associated to the measurement node of the respective combination.

An integrated circuit includes a test circuit, and an analog delay circuit and a sampler register, each configured to receive a signal. The delay circuit includes a configuration input and phases with a final phase. The sampler register includes result outputs and delay inputs that are each coupled to a respective delay output of the phases. The sampler register is configured to output a sample signal indicating a relationship between the signal and at least the final phase of the phases. The integrated circuit further includes a test circuit that includes a configuration output coupled to the configuration input of the delay circuit, and result inputs coupled to the result outputs of the sampler register. The test circuit is configured to iterate through selected values to test the delay circuit and determine that the delay circuit passes the test when the relationship matches a predetermined criterion.

An integrated circuit includes a test circuit, and an analog delay circuit and a sampler register, each configured to receive a signal. The delay circuit includes a configuration input and phases with a final phase. The sampler register includes result outputs and delay inputs that are each coupled to a respective delay output of the phases. The sampler register is configured to output a sample signal indicating a relationship between the signal and at least the final phase of the phases. The integrated circuit further includes a test circuit that includes a configuration output coupled to the configuration input of the delay circuit, and result inputs coupled to the result outputs of the sampler register. The test circuit is configured to iterate through selected values to test the delay circuit and determine that the delay circuit passes the test when the relationship matches a predetermined criterion.

A circuit arrangement comprises a comparator circuit configured for comparing a voltage to a provided reference voltage and a time evaluation circuit configured for determining a time interval between a start signal and a stop signal. The circuit arrangement further comprises a voltage ramp generation circuit configured for generating a voltage ramp beginning with the start signal. In a normal operation mode, the circuit arrangement is configured for comparing an input voltage to the reference voltage by using the comparator circuit. In a self-test mode for performing a self-test of the comparator circuit, the circuit arrangement is configured for generating a voltage ramp by using the voltage ramp generation circuit, for continuously comparing the generated voltage ramp to the reference voltage by using the comparator circuit and for determining a time interval in which the generated voltage ramp reaches the reference voltage by using the time evaluation circuit.

Apparatuses, systems, and methods for, and more particularly to apparatuses, systems, and methods for a high-speed composite amplifier driving circuit to generate and output analog signals. The high-speed composite amplifier driving circuit can combine a voltage-controlled pulser and waveform generator with high-accuracy current-voltage (I-V) measurement functions. The voltage-controlled pulser and waveform generator, for example, can provide a 5 volt, 10 milliamp waveform at up to 50 megahertz with 5 nanosecond rise/fall timing and 8 ns minimum pulse widths. In addition, the high-accuracy I-V measurements can measure a 10 volts, 10 milliamp waveform at up to 30 MHz with 7-10 nanosecond rise/fall timing and 8 to 12 nanosecond minimum pulse widths.

Apparatuses, systems, and methods for, and more particularly to apparatuses, systems, and methods for a high-speed composite amplifier driving circuit to generate and output analog signals. The high-speed composite amplifier driving circuit can combine a voltage-controlled pulser and waveform generator with high-accuracy current-voltage (I-V) measurement functions. The voltage-controlled pulser and waveform generator, for example, can provide a 5 volt, 10 milliamp waveform at up to 50 megahertz with 5 nanosecond rise/fall timing and 8 ns minimum pulse widths. In addition, the high-accuracy I-V measurements can measure a 10 volts, 10 milliamp waveform at up to 30 MHz with 7-10 nanosecond rise/fall timing and 8 to 12 nanosecond minimum pulse widths.