A test and measurement device having a signal source, including an impairment generator configured to output an impairment and a waveform synthesizer. The waveform synthesizer receives an input digital signal to be synthesized, receives the impairment, and synthesizes a synthesized digital signal based on the input digital signal and the impairment. The test and measurement instrument also includes a fixed sample rate digital-to-analog converter configured to receive a clock signal and the synthesized digital signal and output an analog signal.

The present invention is a process by which an engineer can provide as input the design, functional verification goals, and other abstract design details, and receive as output an agent which can be integrated into traditional test benches and will generate stimuli to automatically hit the functional coverage goals for the design. The present invention may employ a system which includes a learning configurator, a learning-based test generator, and a test bench. The learning test generator is communicatively coupled to the generator and notably comprises a learning algorithm.

Systems and methods are provided for blended analog-to-digital conversion for digital test and measurement devices. A first-frequency-domain circuit path is configured to generate a first processed digital signal having high fidelity to an analog signal over a first frequency domain. A second-frequency-domain circuit path is configured to generate a second processed digital signal having high fidelity to the analog signal over a second frequency domain. A blended digital signal is generated using the first processed digital signal and the second processed digital signal. The blended digital signal can have high fidelity to the analog signal over multiple frequency domains.

Systems and methods are provided for blended analog-to-digital conversion for digital test and measurement devices. A first-frequency-domain circuit path is configured to generate a first processed digital signal having high fidelity to an analog signal over a first frequency domain. A second-frequency-domain circuit path is configured to generate a second processed digital signal having high fidelity to the analog signal over a second frequency domain. A blended digital signal is generated using the first processed digital signal and the second processed digital signal. The blended digital signal can have high fidelity to the analog signal over multiple frequency domains.

A test system is provided. The test system includes a printed circuit board (PCB) and a plurality of integrated circuits (ICs) mounted on the PCB. A first IC of the plurality includes a first test circuit having a first test access port (TAP) controller. A second IC of the plurality includes a second test circuit having a second TAP controller and an embedded tester having a test data output coupled to a test data input of the first TAP controller by way of a link circuit. The embedded tester is configured to provide test control signals to the first TAP controller and the second TAP controller.

An integrated circuit test apparatus includes: a first test unit configured to output a current for a built-in self test (BIST) progress state for each internal circuit of an integrated circuit in a BIST test mode and to determine whether each internal circuit operates normally in a wake-up mode of the integrated circuit; and a first determination module configured to determine whether each internal circuit is in a stuck state based on a change detected by the first test unit.

According to one embodiment, a semiconductor device performs processing based on a user program by using a user program, which is used in a normal mode, as an analysis program and making a plurality of peripheral circuits having the same function operate in lock-step where the plurality of peripheral circuits operate in the identical manner, and makes failure diagnosis of the peripheral circuits by determining match or mismatch of a plurality of analysis information respectively obtained from the plurality of peripheral circuits operating in lock-step.

According to one embodiment, a semiconductor device performs processing based on a user program by using a user program, which is used in a normal mode, as an analysis program and making a plurality of peripheral circuits having the same function operate in lock-step where the plurality of peripheral circuits operate in the identical manner, and makes failure diagnosis of the peripheral circuits by determining match or mismatch of a plurality of analysis information respectively obtained from the plurality of peripheral circuits operating in lock-step.

A test apparatus may include transceivers and a global de-skew circuit. In a training mode, the transceivers provide first timing information obtained by delaying a first data signal in the range of up to a preset unit interval based on a clock signal and receive second timing information corresponding to timing differences between a slowest transceiver and the remaining transceivers. In an operation mode, the transceivers provide compensation data to a plurality of DUTs (Devices Under Test) substantially simultaneously. The compensation data may be obtained by delaying a second data signal by multiples of the preset unit interval in response to the second timing information. In the training mode, the global de-skew circuit receives the first timing information, calculates, using the first timing information, the timing differences between the slowest transceiver and the remaining transceivers , and provides the second timing information corresponding to the timing differences to the transceivers.

A test apparatus may include transceivers and a global de-skew circuit. In a training mode, the transceivers provide first timing information obtained by delaying a first data signal in the range of up to a preset unit interval based on a clock signal and receive second timing information corresponding to timing differences between a slowest transceiver and the remaining transceivers. In an operation mode, the transceivers provide compensation data to a plurality of DUTs (Devices Under Test) substantially simultaneously. The compensation data may be obtained by delaying a second data signal by multiples of the preset unit interval in response to the second timing information. In the training mode, the global de-skew circuit receives the first timing information, calculates, using the first timing information, the timing differences between the slowest transceiver and the remaining transceivers , and provides the second timing information corresponding to the timing differences to the transceivers.