A method includes receiving tester configuration data, test pattern data, and tester operation data; configuring a circuit for performing a designated test evaluation; generating a stimulus waveform; converting the stimulus waveform to an analog stimulus signal; transferring the analog stimulus signal to a first terminal of a MTJ DUT at reception of a trigger timing signal; generating time traces based on the trigger timing signal; generating a response signal at a second terminal of the MTJ DUT and across a termination resistor as the analog stimulus signal is transferred through the MTJ DUT; converting the response signal to a digitized response signal indicating its voltage amplitude; and performing the designated test evaluation and analysis function in the configurable circuit based on voltage amplitudes and time values of the stimulus waveform, the digitized response signal, and the timing traces.

A method includes receiving tester configuration data, test pattern data, and tester operation data; configuring a circuit for performing a designated test evaluation; generating a stimulus waveform; converting the stimulus waveform to an analog stimulus signal; transferring the analog stimulus signal to a first terminal of a MTJ DUT at reception of a trigger timing signal; generating time traces based on the trigger timing signal; generating a response signal at a second terminal of the MTJ DUT and across a termination resistor as the analog stimulus signal is transferred through the MTJ DUT; converting the response signal to a digitized response signal indicating its voltage amplitude; and performing the designated test evaluation and analysis function in the configurable circuit based on voltage amplitudes and time values of the stimulus waveform, the digitized response signal, and the timing traces.

A measuring system has an analog-to-digital converter, an acquisition memory, a processing unit, and a display memory. The processing unit is adapted to decode a digital signal according to a protocol creating a decoded signal and to evaluate the decoded signal at a cursor position. The digital data generated by decoding the decoded signal at the cursor position is stored in the display memory. Further, a method for analyzing an analog signal according to a protocol is shown.

A measuring system has an analog-to-digital converter, an acquisition memory, a processing unit, and a display memory. The processing unit is adapted to decode a digital signal according to a protocol creating a decoded signal and to evaluate the decoded signal at a cursor position. The digital data generated by decoding the decoded signal at the cursor position is stored in the display memory. Further, a method for analyzing an analog signal according to a protocol is shown.

Embodiments disclosed herein are directed towards systems and methods for electric current leakage detection in a land seismic system. Embodiments may include generating at least one test signal using a digital to analog converter DAC circuitry, wherein the DAC circuitry includes an output operatively connected to earth ground. Embodiments may further include alternately grounding a positive path to an analog to digital converter ADC circuitry during a first time window and a negative path to the analog to digital converter during a second time window while measuring an ADC signal. Embodiments may also include determining an average amplitude of the first time window and the second time window and determining a leakage resistance based upon, at least in part, the average amplitude of the first time window and the second time window.

Embodiments disclosed herein are directed towards systems and methods for electric current leakage detection in a land seismic system. Embodiments may include generating at least one test signal using a digital to analog converter DAC circuitry, wherein the DAC circuitry includes an output operatively connected to earth ground. Embodiments may further include alternately grounding a positive path to an analog to digital converter ADC circuitry during a first time window and a negative path to the analog to digital converter during a second time window while measuring an ADC signal. Embodiments may also include determining an average amplitude of the first time window and the second time window and determining a leakage resistance based upon, at least in part, the average amplitude of the first time window and the second time window.

A mixed signal testing system capable of testing differently configured units under test (UUT) includes a controller, a test station and an interface system that support multiple UUTs. The test station includes independent sets of channels configured to send signals to and receive signals from each UUT being tested and signal processing subsystems that direct stimulus signals to a respective set of channels and receive signals in response thereto. The signal processing subsystems enable simultaneous and independent directing of stimulus signals through the sets of channels to each UUT and reception of signals from each UUT in response to the stimulus signals. Received signals responsive to stimulus signals provided to a fully functional UUT (with and without induced faults) are used to assess presence or absence of faults in the UUT being tested which may be determined to include one or more faults or be fault-free, i.e., fully functional.

An integrated circuit device is disclosed. The device includes a circuit configured to perform a function, a fault management component, at least one user register, an analog test bus component, a built-in self-test component, a safety monitor component, and gating logic. Additionally, the circuit is separated from the fault management component, the at least one user register, the analog test bus component, the built-in self-test component, the safety monitor, and the gating logic.

An integrated circuit device is disclosed. The device includes a circuit configured to perform a function, a fault management component, at least one user register, an analog test bus component, a built-in self-test component, a safety monitor component, and gating logic. Additionally, the circuit is separated from the fault management component, the at least one user register, the analog test bus component, the built-in self-test component, the safety monitor, and the gating logic.

Certain aspects of the disclosure are directed toward test control and test access configuration via two pins on an integrated circuit (IC). According to a specific example, an IC chip-based apparatus is used in connection with a controller for testing a target IC. The IC chip-based apparatus includes an event (capture) circuit configured and arranged to control logic states through which a static test configuration is selected for a given event detected in response to a clock signal and to a data signal respectively derived from the controller. A test-operation control circuit may be configured and arranged to test the target IC by selectively configuring each of the clock pin and the I/O pin of the controller for use as an analog test bus, data input to the controller or data output from the controller, and carrying out dynamic operations by communicating test signals via pins of the target IC.