The disclosure provides a method and apparatus of interleaved on-chip testing. The method merges a test setup for analog components with a test setup for digital components and then interleaves the execution of the digital components with the analog components. This provides concurrency via a unified mode of operation. The apparatus includes a system-on-chip test access port (SoC TAP) in communication with a memory test access port (MTAP). A built-in self-test (BIST) controller communicates with the MTAP, a physical layer, and a memory. A multiplexer is in communication with the memory and a phase locked loop (PLL) through an AND gate.

An electronic circuit includes first and second channels which respectively receive first and second analog signals. The first channel includes a first digital to analog converter having an output coupled to a first input of a first sign comparator, and the second channel includes a second digital to analog converter. A switch network selectively couples, upon reception of a self-test mode signal signaling a test phase, an output of the second digital to analog converter to a second input of the first sign comparator. A ramp generation circuit supplies to the first digital to analog converter and the second digital to analog converter two identical ramps of digital codes, which are shifted by a programmable offset with respect to one another. A checking circuit issues a test status signal based on the output of the first sign comparator.

The present disclosure provides a DFT architecture for ICs and a method for testing the ICs with the proposed DFT architecture. The present disclosure also includes a focus on USB PD protocol with respect to the DFT architecture. The present disclosure also includes focus on testing IC with single I/O pin. The DFT architecture primarily comprises of a test mode controller and reuses the USBPD protocol framework logic comprising analog USBPD CC circuitry in analog block and the USBPD signaling, protocol logic in digital block for the test purposes. The DFT architecture is implemented with analog test modes and digital test modes using a single I/O pin, wherein analog test modes comprises of analog trims and observation modes and digital test modes comprises of LBIST, ATPG and digital observation modes. The method disclosed is directed to the functions associated with testing the USBPD ICS using single I/O pin.

Provided test method and apparatus of communication chip, device and medium. The test method of communication chip includes receiving end test method and transmitting end test method. The receiving end test method of the communication chip includes: an idle time slot of the receiving end of the communication chip is detected in a running process of the communication chip; a test vector is generated, and a standard result corresponding to the test vector is generated; a data frame containing the test vector is constructed, and the data frame is sent to the receiving end of the communication chip in the idle time slot to enable the receiving end of the communication chip to process the data frame; and a chip processing result uploaded by the receiving end of the communication chip is received, and the standard result is compared with the chip processing result.

Systems, compute-implemented methods, and computer program products to facilitate automated waveform validation are provided. According to an embodiment, a system can comprise a processor that executes computer executable components stored in memory. The computer executable components comprise a waveform comparison component that compares a digital conversion of an analog signal to a reference signal.

A test and measurement device includes an input configured to receive an analog signal from a Device Under Test (DUT), an Analog to Digital Converter (ADC) coupled to the input and structured to convert the analog signal to a digital signal, a receiver implemented in a first Field Programmable Gate Array (FPGA) and structured to accept the digital signal and perform signal analysis on the digital signal, a transmitter implemented in a second FPGA and structured to generate a digital output signal, and a Digital to Analog Converter (DAC) coupled to the transmitter and structured to convert the digital output signal from the transmitter to an analog signal, and structured to send the analog signal to the DUT. The receiver and the transmitter are coupled together by a high speed data link over which data about the current testing environment may be shared.

The present disclosure relates to a sensor circuit having a first interface configured to receive a first sensor signal in response to a first measurement of a first physical quantity, a first analog-to-digital converter configured to sample the first sensor signal to generate a sampled first sensor signal, a second interface configured to receive a second sensor signal in response to a second measurement of the same first physical quantity, a third interface configured to receive at least one third sensor signal in response to at least one third measurement of at least one second physical quantity that is different from the first physical quantity, a multiplexer configured to multiplex the second and the at least one third sensor signal to a multiplexed sensor signal, and a second analog-to-digital converter coupled to the multiplexer and configured to sample the multiplexed sensor signal to generate a sampled multiplexed sensor signal.

The present disclosure relates to a sensor circuit having a first interface configured to receive a first sensor signal in response to a first measurement of a first physical quantity, a first analog-to-digital converter configured to sample the first sensor signal to generate a sampled first sensor signal, a second interface configured to receive a second sensor signal in response to a second measurement of the same first physical quantity, a third interface configured to receive at least one third sensor signal in response to at least one third measurement of at least one second physical quantity that is different from the first physical quantity, a multiplexer configured to multiplex the second and the at least one third sensor signal to a multiplexed sensor signal, and a second analog-to-digital converter coupled to the multiplexer and configured to sample the multiplexed sensor signal to generate a sampled multiplexed sensor signal.

Device for checking the integrity of a digital transmission for an analog output of a system. The analog output may be checked for transient errors that can be attributed to a digital transmission path embedded somewhere within the vehicle system. A test signal is introduced into a digital transmission that can be reassembled from an analog path of the analog output, and, if not, allows the test device to pinpoint that errors are appearing due to the digital path, and not because of the analog output. In this way, debugging an installation of a system becomes easier; obtaining confidence in reliability of a mixed analog and digital system becomes less of a challenge and less time consuming.

Device for checking the integrity of a digital transmission for an analog output of a system. The analog output may be checked for transient errors that can be attributed to a digital transmission path embedded somewhere within the vehicle system. A test signal is introduced into a digital transmission that can be reassembled from an analog path of the analog output, and, if not, allows the test device to pinpoint that errors are appearing due to the digital path, and not because of the analog output. In this way, debugging an installation of a system becomes easier; obtaining confidence in reliability of a mixed analog and digital system becomes less of a challenge and less time consuming.