A method may involve applying, by a testing computing device, a distortion to a computing device under test. The distortion includes operating the computing device under test at a performance range of a computational resource that could cause the computing device under test to operate outside a normal range. The method may also involve receiving, by the testing computing device and in response to the applying of the distortion, one or more digital signals from the computing device under test. The method may further involve comparing, by the testing computing device, the one or more digital signals to one or more baseline digital signals associated with the computing device under test. The method may also involve detecting, based on the comparing, a presence of at least one anomalous element that could be indicative of a hostile element in the computing device under test.

The present disclosure provides a semiconductor wafer. The semiconductor wafer includes: a scribe line between a first row of dies and a second row of dies; and a benchmark circuit disposed adjacent to the scribe line and electrically coupled to a first conductive contact and a second conductive contact. The benchmark circuit includes a first device-under-test (DUT); a second DUT; a first switching circuit configured to selectively couple the first DUT and the second DUT to the first conductive contact; and a second switching circuit configured to selectively couple the first DUT and the second DUT to the second conductive contact.

An optoelectronic chip includes optical inputs having different passbands, a photonic circuit to be tested, and an optical coupling device configured to couple said inputs to the photonic circuit to be tested.

The present disclosure provides a method and an apparatus of testing a circuit, and a storage medium. The method of testing a circuit includes: determining a preset circuit module in a to-be-tested circuit and a preset node in the preset circuit module; inputting a test signal to an input terminal of the to-be-tested circuit according to a preset input rule, and obtaining a signal of the preset node in the preset circuit module; and determining a status of the preset circuit module based on the obtained signal of the preset node.

Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.

Compensating for signal loss, including determining a first expected loss at a first frequency and a second expected loss at a second frequency at a receiver associated with a first lane of a PCB; calculating an expected rate of change of signal loss between the first and the second frequencies based on the first and the second expected losses; calculating a first measured loss of a first signal transmitted at the first frequency and a second measured loss of a second signal transmitted at the second frequency from a transmitter to the receiver along the first lane of the PCB; calculating a measured rate of change of signal loss between the first and second frequencies based on the first and the second measured losses; comparing the measured rate of change with the expected rate of change; compensating a gain of a signal transmitted from the transmitter to the receiver.

Techniques and mechanisms to exchange test, debug or trace (TDT) information via a general purpose input/output (I/O) interface. In an embodiment, an I/O interface of a device is coupled to an external TDT unit, wherein the I/O interface is compatible with an interconnect standard that supports communication of data other than any test information, debug information or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I/O interface. Information exchanged via the I/O interface is generated by, or results in, the performance of one or more TDT operations to evaluate the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I/O interface with a test access point that is coupled between the one or more circuit components and the I/O interface.

A test and measurement instrument includes one or more ports including at least one test port configured to couple to one or more devices under test, a user interface to receive one or more user inputs, an acquisition memory to store waveform data acquired from the one or more devices under test, one or more processors configured to execute code that causes the one or more processors to: receive an input through the user interface; determine one or more requested data types based on the input; transform the waveform data into compressed data containing only data elements corresponding to the one or more requested data types; and transmit the compressed data to a client. A method of providing usage-aware compressed data from a test and measurement instrument includes acquiring waveform data from one or more devices under test, receiving a user input through a user interface, determining one or more requested data types based on the user input, transforming the waveform data into compressed data containing only data elements corresponding to the one or more requested data types, and transmitting the compressed data to a client.

A system and method are provided for displaying input signals from a DUT on a display screen. The method includes sending a data stream of digitized data received from the DUT to an FPGA for serial decoding; receiving decoded symbols from the FPGA; identifying valid symbols among the decoded symbols indicating transitions between the decoded symbols; storing the valid symbols with corresponding time-tags as valid packets in memory, and discarding ones of the decoded symbols occurring between the valid symbols; and plotting on the display screen the valid packets occurring between beginning and ending valid packets of the stored valid packets. The beginning valid packet has a corresponding time-tag occurring immediately before a first point time-tag associated with a left edge of the display screen, and the ending valid packet has a corresponding time-tag occurring at or immediately before a last point time-tag associated with a right edge of the display screen.

A system and method are provided for displaying input signals from a DUT on a display screen. The method includes sending a data stream of digitized data received from the DUT to an FPGA for serial decoding; receiving decoded symbols from the FPGA; identifying valid symbols among the decoded symbols indicating transitions between the decoded symbols; storing the valid symbols with corresponding time-tags as valid packets in memory, and discarding ones of the decoded symbols occurring between the valid symbols; and plotting on the display screen the valid packets occurring between beginning and ending valid packets of the stored valid packets. The beginning valid packet has a corresponding time-tag occurring immediately before a first point time-tag associated with a left edge of the display screen, and the ending valid packet has a corresponding time-tag occurring at or immediately before a last point time-tag associated with a right edge of the display screen.