A debug system for debugging a logic design includes an adaptor and a debug station connected to the adaptor. The logic design includes a plurality of design modules. The adaptor is configured to receive an emulation output of the logic design. The emulation output includes a design snapshot of the logic design and input signals to the logic design that both are recorded during an emulation process of the logic design. The debug station is configured to generate, based on the emulation output and a netlist of a design module of the logic design, an emulation history of the design module.

The invention relates to a method, an apparatus and a non-transitory computer-readable storage medium for debugging a solid-state disk (SSD) device. The method is performed by a processing unit of a single-board personal computer (PC) when loading and executing a function of a runtime library, to include: receiving a request to drive a General-Purpose Input/Output (GPIO) interface (I/F), which includes a parameter required for completing a Joint Test Action Group (JTAG) command; issuing a first hardware instruction to the GPIO I/F to set a register corresponding to a GPIO test data input (TDI) pin according to the parameter carried in the request for emulating to issue the JTAG command to a solid-state disk (SSD) device, wherein the single-board PC is coupled to the SSD device through the GPIO I/F; issuing a second hardware instruction to the GPIO I/F to read a value of the register corresponding to the GPIO TDI pin; and replying with a completion message in response to the request.

A semiconductor device includes a control signal generating circuit, a first circuit and a second circuit. The control signal generating circuit is configured to generate a control signal. The first circuit is coupled to the control signal generating circuit and configured to receive the control signal and generate a first test pulse signal according to the control signal. The second circuit is coupled to the control signal generating circuit and the first circuit and configured to receive the control signal and generate a second test pulse signal according to the control signal. The first circuit is comprised in the first block. The second circuit is comprised in the second block. The first block and the second block are connected with each other via one or more interconnection logics and timing of the first test pulse signal and timing of the second test pulse signal are synchronized.

The present invention relates to a device (1) such as a connected object comprising a first electronic circuit (2) comprising: a first processing unit (6) for executing a program, a first memory (8) for memorizing data during the execution of the program, a debug port (10) dedicated to checking the execution of the program from outside the first circuit,
a second electronic circuit (4) connected to the debug port (10), comprising: a second memory (14) memorizing reference data related to the program, a second processing unit (12) for implementing the following steps automatically and autonomously via the debug port (10): checking the integrity of the data memorized by the first memory (8) and/or the compliance of the program's execution by the first processing unit (6) with a reference execution, assisted by the reference data.

In an information processing apparatus, a control unit receives operation instructions. Each time receiving an operation instruction, the control unit detects the number of operating circuits that are to operate in accordance with the received operation instruction, in a circuit group of circuits that operate in synchronization with a clock signal. In addition, each time receiving an operation instruction, the control unit determines whether power supply noise that is likely to cause a timing error in the circuit group will occur, on the basis of a result of comparing an increase in the number of operating circuits per prescribed time period with a threshold, and lowers the frequency of the clock signal when determining that the power supply noise will occur.

The present invention relates a method and apparatus for setting a test configuration. A test device for testing a device under test is identified, and the measurement interfaces of the test device are assigned to appropriate measurement points of the device under test. The configuration of the test scenario is established by generating a representation of the test device and the connections between the interface of the test device and the related measurement points.

Provided are a clock conversion device, a test system including the same, and a method of operating the test system. The clock conversion device includes a first clock generator configured to receive a first input clock signal from test logic and generate a first clock signal of which a frequency is multiplied and a phase is locked; a clock conversion circuit configured to receive the first clock signal and generate one or more second clock signals by converting at least one clock characteristic of the first clock signal; and an output selector configured to output any one of the first clock signal and the one or more second clock signals as an output clock signal, wherein the clock conversion device is configured to provide the output clock signal to a device under test (DUT).

A power supply is configured to perform an at least partial compensation of a voltage variation caused by a load change using a voltage variation compensation mechanism which is triggered in response to an expected load change. An Automated test equipment for testing a device under test comprises a power supply, which is configured to supply the device under test. The automated test equipment comprises a pattern generator configured to provide one or more stimulus signals for the device under test. The power supply is configured to perform an at least partial compensation of a voltage variation caused by a load change using a voltage variation compensation mechanism which is activated in synchronism with one or more of the stimulus signals and/or in response to one or more response data signals from the device under test. Corresponding methods and a computer program are also described.

A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.

The present invention discloses a hysteresis signal detection circuit, comprising: a first MOS transistor, a second MOS transistor, an inverter INV1, an inverter INV2 and an inverter INV3. A gate of the first MOS transistor is connected with an input end, and a drain of the first MOS transistor is connected with an output end through the inverter INV1, the inverter INV2 and the inverter INV3 successively; a source of the first MOS transistor is connected with a drain of the second MOS transistor, and a gate of the second MOS transistor is connected between the inverter INV1 and the inverter INV2; and a resistor R1 is connected between a source and the drain of the second MOS transistor. In the present invention, not only the hysteresis voltage can be adjusted through current and resistance values, which is flexible, but also the hysteresis voltage may not change with power voltage.