An electrical device having a clocked circuitry, and a method for testing the power supply unit of the electrical device. The electrical device comprises an electrical load, a clocked power supply unit, at least one pulse transformer and an evaluation device. The power supply unit comprises a power stack having at least one power semiconductor switch and is configured for generating a clocked voltage for the electrical load from an electric voltage based on an alternating on/off switching of the power semiconductor switch. The power stack exhibits at least one current path, through which an electric current flows during operation. The pulse transformer generates a signal assigned to the change in the charge and/or the direction of the electric current flowing through the current path. The evaluation device evaluates the signal coming from the pulse transformer and draws a conclusion regarding the operational reliability of the power semiconductor switch.

A power module includes a first MOS transistor and a first Schottky barrier diode for a lower arm, and a second MOS transistor and a second Schottky barrier diode for an upper arm. In one embodiment, one positive-side power supply terminal and one negative-side power supply terminal are provided, while an output terminal to which the first and second MOS transistors are connected and an output terminal to which the first and second Schottky barrier diodes are connected are provided as separate output terminals.

A power module includes a first MOS transistor and a first Schottky barrier diode for a lower arm, and a second MOS transistor and a second Schottky barrier diode for an upper arm. In one embodiment, one positive-side power supply terminal and one negative-side power supply terminal are provided, while an output terminal to which the first and second MOS transistors are connected and an output terminal to which the first and second Schottky barrier diodes are connected are provided as separate output terminals.

To reduce the rate at which a false alternating current (“AC”) loss alarming signal is generated, but at the same time detect an actual AC loss situation in a timely manner, the disclosed method describes an AC line power loss detection and active verification method. If the AC line input voltage dips momentarily lower than a standard sine wave amplitude, the AC line may not be considered lost as long as it still has energy to drive a load. The method inserts a momentary load across the AC line and compares the AC line voltage before and after the extra load is applied. If the AC power is present, this extra loading will increase the AC loading current momentarily, but will not affect the AC line voltage. However, if the AC power is lost, such loading will lower the AC line voltage, indicating a loss of power.

To reduce the rate at which a false alternating current (“AC”) loss alarming signal is generated, but at the same time detect an actual AC loss situation in a timely manner, the disclosed method describes an AC line power loss detection and active verification method. If the AC line input voltage dips momentarily lower than a standard sine wave amplitude, the AC line may not be considered lost as long as it still has energy to drive a load. The method inserts a momentary load across the AC line and compares the AC line voltage before and after the extra load is applied. If the AC power is present, this extra loading will increase the AC loading current momentarily, but will not affect the AC line voltage. However, if the AC power is lost, such loading will lower the AC line voltage, indicating a loss of power.

A method for monitoring a change in a capacitance in an electric system, and an electric system comprising a multilevel inverter and at least two capacitances connected in series between a negative DC pole and a positive DC pole of the inverter, wherein the connection point between the capacitances is connected to one of the at least one middle DC pole of the inverter, and a controller configured to provide by the inverter an AC current component to one of the at least one middle DC pole of the inverter, which AC current component is distributed between the two capacitances connected to the middle DC pole, and monitor resulting AC voltage components in the two capacitances, and determine on the basis of a difference between the monitored AC voltage components a change in at least one of the two capacitances.

A system and a method of detecting and isolating a fault in an electric motor system are provided. The method includes detecting, at a motor drive electronics (MDE) component that is configured to drive an electric motor through a harnessing, the fault in the electric motor system, applying a voltage and current, at the MDE component, according to a gate switching sequence for all phases of the electric motor system in response to detecting the fault, sensing voltage and current values in the MDE component between switches of an inverter of the MDE component, and isolating the fault within the electric motor system based on the sensed voltage and current values.

A method for evaluation of switched reluctance motor system reliability through quantitative analysis of a three-level Markov model. Through analysis of the operating condition of switched reluctance motor drive system under first-level faults, second-level faults and third-level faults, 4 valid states and 1 invalid state under first-level faults, 14 valid states and 4 invalid states under second-level faults, and 43 valid states and 14 invalid states under third-level faults are obtained. If initial normal state and final invalid state are also considered, a three-level Markov model will have 62 valid states and 20 invalid states in total. A state transition diagram of the switched reluctance motor drive system under three-level faults is established, a state transition matrix is obtained, a probability matrix of the system in valid states is attained, the sum of all elements of the probability matrix is calculated, and MTTF is obtained from a reliability function.

A method for determining the remaining usability of a semiconductor module in normal use. The semiconductor module is thermally coupled to a cooling device. A predefined electrical load is applied to the semiconductor module while predefined cooling is effected by the cooling device. A temperature of a semiconductor element of the semiconductor module is sensed at least for the predefined electrical load on the semiconductor module. The sensed temperature is compared with a comparison temperature in a first comparison. The comparison temperature is assigned to the predefined electrical load with the predefined cooling, and prediction data for the remaining usability of the semiconductor module in normal use up to a usability end are determined at least in accordance with the first comparison.

A method for testing a lifetime of a surface state carrier of a semiconductor, including the following steps, 1) a narrow pulse light source is used to emit a light pulse, and coupled to an interior of a near-field optical probe, and the near-field optical probe produces a photon-generated carrier on a surface of a semiconductor material under test through excitation. 2) The excited photon-generated carrier is concentrated on the surface of the semiconductor material, and recombination is conducted continuously with a surface state as a recombination center. 3) A change in a lattice constant is produced due to an electronic volume effect, a stress wave is produced, and a signal of the stress wave is detected in a high-frequency broadband ultrasonic testing mode. 4) Fitting calculation is conducted on the signal of the stress wave to obtain the lifetime of the surface state carrier τ.sub.c.