A driver circuit arrangement for driving a transistor bridge, which includes at least a first half-bridge composed of a low-side transistor and a high-side transistor, is described herein. In accordance with one example of the description, the circuit includes a current source and a detection circuit. The current source is operably coupled to the high-side transistor of the first half-bridge and configured to supply a test current to the first half bridge. The detection circuit is configured to compare a voltage sense signal, which represents the voltage across the high-side transistor of the first half-bridge, with at least one first threshold to detect, dependent on the result of this comparison, whether a short-circuit is present in the first half-bridge.

A motor drive device includes a power source unit rectifying AC voltage to DC voltage and to smooth the DC voltage by a capacitor, a motor drive amplification, a power source voltage measurement unit, an insulation resistance deterioration detection unit having a contact unit connecting one end of the capacitor to the ground and a current detection unit provided between the other end of the capacitor and a motor coil, and detecting a deterioration in an insulation resistance of the motor based on a detected signal obtained from a closed circuit formed by the contact unit, the capacitor, the motor coil, and the ground by using the current detection unit, and a failure detection unit detecting a failure in the insulation resistance deterioration detection unit based on the detected signal in the insulation resistance deterioration detection unit and a voltage value measured by the power source voltage measurement unit.

A method for testing an inverter having a bridge comprising a first switch (T1) arranged between a positive connection (DC+) of a divided link circuit, having a center point (M), and a positive inner connection (PI), a second switch (T2) arranged between the positive inner connection (PI) and a bridge output (BR), a third switch (T3) arranged between the bridge output (BR) and a negative inner connection (NI), a fourth switch (T4) arranged between the negative inner connection (NI) and a negative connection (DC−) of the divided link circuit, a fifth switch (T5) arranged between the center point (M) and the positive inner connection (PI), and a sixth switch (T6) arranged between the center point (M) and the negative inner connection (NI) is disclosed. A grid filter having a filter inductor (LF) and a filter capacitor (CF) is connected to the bridge output (BR). The method comprises applying a link circuit voltage to the divided link circuit, while the bridge output (BR) is isolated from a connected grid using the connected grid filter, fully discharging the filter capacitor (CF), closing the first switch (T1) and the sixth switch (T6), while the fourth switch (T4) and the fifth switch (T5) are open, subsequently clocking the second switch (T2) using a plurality of short pulses, wherein the duty cycle of the short pulses is predetermined between 1% and 5%, subsequently to the clocking determining a voltage dropped across the filter capacitor (CF) and identifying a fault state of the bridge when the voltage dropped is outside of a voltage window with an upper window limit and a lower window limit. An inverter is also disclosed, which has a control system designed and set up to execute the method according to one of the preceding claims and to connect the inverter to a connected grid only if a fault state is not identified.

A method for testing an inverter having a bridge comprising a first switch (T1) arranged between a positive connection (DC+) of a divided link circuit, having a center point (M), and a positive inner connection (PI), a second switch (T2) arranged between the positive inner connection (PI) and a bridge output (BR), a third switch (T3) arranged between the bridge output (BR) and a negative inner connection (NI), a fourth switch (T4) arranged between the negative inner connection (NI) and a negative connection (DC−) of the divided link circuit, a fifth switch (T5) arranged between the center point (M) and the positive inner connection (PI), and a sixth switch (T6) arranged between the center point (M) and the negative inner connection (NI) is disclosed. A grid filter having a filter inductor (LF) and a filter capacitor (CF) is connected to the bridge output (BR). The method comprises applying a link circuit voltage to the divided link circuit, while the bridge output (BR) is isolated from a connected grid using the connected grid filter, fully discharging the filter capacitor (CF), closing the first switch (T1) and the sixth switch (T6), while the fourth switch (T4) and the fifth switch (T5) are open, subsequently clocking the second switch (T2) using a plurality of short pulses, wherein the duty cycle of the short pulses is predetermined between 1% and 5%, subsequently to the clocking determining a voltage dropped across the filter capacitor (CF) and identifying a fault state of the bridge when the voltage dropped is outside of a voltage window with an upper window limit and a lower window limit. An inverter is also disclosed, which has a control system designed and set up to execute the method according to one of the preceding claims and to connect the inverter to a connected grid only if a fault state is not identified.

The instant disclosure provides a power supply system and control method thereof. The power supply system comprises at least two power supplies electrically coupled in parallel. The control unit of the power supply generates a wake-up signal or a sleep signal according to the loading status. A second communication port of each power supply is coupled to a first communication port of the next stage power supply to establish cascading communications architecture. The first communication port receives a wake-up signal from the second communication port of the previous stage power supply and outputs a sleep signal to the second communication port of the previous stage power supply. The second communication port receives the sleep signal from the first communication port of the next stage power supply and outputs the wake-up signal to the first communication port of the next stage power supply.

The instant disclosure provides a power supply system and control method thereof. The power supply system comprises at least two power supplies electrically coupled in parallel. The control unit of the power supply generates a wake-up signal or a sleep signal according to the loading status. A second communication port of each power supply is coupled to a first communication port of the next stage power supply to establish cascading communications architecture. The first communication port receives a wake-up signal from the second communication port of the previous stage power supply and outputs a sleep signal to the second communication port of the previous stage power supply. The second communication port receives the sleep signal from the first communication port of the next stage power supply and outputs the wake-up signal to the first communication port of the next stage power supply.

A current leakage detector for detecting current leakage between a power source and a load including a first sensing coil and a second sensing coil positioned opposite the first sensing coil. The current leakage detector further includes a magnetic field sensor proximate the first sensing coil and the second sensing coil and the magnetic field sensor has a response range. The current leakage detector also includes a bias circuit configured to adjust the response range of the magnetic field sensor. A method for detecting current leakage includes providing a first sensing coil and a second sensing coil. The method continues with the steps of providing a magnetic field sensor in proximity to the first and second sensing coils and providing a bias circuit. The method continues with the step of utilizing the bias circuit to place the response of the magnetic field sensor within a preferred response range.

Uninterruptible power supplies (UPSs) are provided including a processor and a voltage sensor circuit in communication with the processor. The voltage sensor circuit is configured to sense a center point voltage (CPV) of a battery module associated with the UPS and provide the sensed CPV to the processor. The processor is configured to receive the sensed CPV of the battery module, determine if the CPV is less than a predetermined voltage and turn off all battery chargers associated with the battery module if the CPV is determined to be less than the predetermined voltage.

The present invention is directed at a method for evaluating the degradation level of capacitors of a power filter connected to an adjustable speed drive (ASD) or a power converter. The invention is also directed at an adjustable speed drive and a power converter provided for performing the method.

Multiphase trans-inductor voltage regulator fault diagnostic. One example is a method of detecting electrical faults in a multiphase power converter, the method comprising: driving, by a controller of the multiphase power converter, a first phase of the power converter, the first phase comprising a phase-one transformer module; driving, by the controller, a second phase of the power converter, the second phase comprising a phase-two transformer module distinct from the phase-one transformer module; testing, by the controller of the multiphase power converter, for a phase-one electrical fault associated with the phase-one transformer module; testing, by the controller, for a phase-two electrical fault associated with the phase-two transformer module; and driving, by the controller, a fault indicator in the presence of a phase-one or phase-two electrical fault.