A performance management scheme for a processor based on leakage current measurement in field. The scheme performs the operations of detection and correction. The operation of detection measures per core leakage current in the field (e.g., using voltage regulator electrical current counters). The operation of correction changes the processor power management behavior. For example, processor cores showing high leakage degradation may be logically swapped with cores showing low leakage degradation.

A method of determining a fault in a protected zone of a power line comprises obtaining measurements at a measurement point at one end of the power line, processing the measurements in a number of parallel processing branches comprising at least two parallel processing branches, wherein the processing in each branch comprises filtering the measurements in a corresponding low pass filter for obtaining a corresponding set of filtered measurements, wherein the cut-off frequencies of the low pass filters in these parallel processing branches differ from each other, performing reach calculations on the filtered measurements for obtaining corresponding reach point quantities, and comparing the reach point quantities with corresponding thresholds. Finally, it is determined that there is a fault within the protected zone if any threshold is crossed.

A ground fault circuit interrupter is provided, including a main control chip, a tripping unit and a self-test detection unit, wherein the tripping unit is connected with the self-test detection unit at a detection point and coupled with a load circuit; the self-test detection unit is coupled with the main control chip, and configured to detect a signal at the detection point and output the signal to the main control chip; the main control chip is coupled with the self-test detection unit, and configured to in a self-test state, simulate a circuit fault, perform self-test, and determine whether the circuit fault could be detected and an alarm signal response to the circuit fault is generated, based on the signal. A self-test function and alarm function response to a circuit fault in a ground fault circuit interrupter can be tested during a final test of production.

A ground fault detection circuit can include a band-pass filter that can have a first node and a second node that can be coupled to an earth ground. The first node can be coupled to a local ground of an automatic test equipment (ATE) system for an electrical device that can be coupled via at least one wire to the ATE. The band-pass filter can be configured to pass and amplify a test current signal established at the first node in response to a coupling of one of a conductor of the at least one wire carrying the test current signal to the local ground, and a conductive element of the electrical device carrying the test current signal to the local ground. A fault alert signal can be provided to provide an indication of ground fault based on a comparison of the amplified test current signal.

A ground fault detection circuit can include a band-pass filter that can have a first node and a second node that can be coupled to an earth ground. The first node can be coupled to a local ground of an automatic test equipment (ATE) system for an electrical device that can be coupled via at least one wire to the ATE. The band-pass filter can be configured to pass and amplify a test current signal established at the first node in response to a coupling of one of a conductor of the at least one wire carrying the test current signal to the local ground, and a conductive element of the electrical device carrying the test current signal to the local ground. A fault alert signal can be provided to provide an indication of ground fault based on a comparison of the amplified test current signal.

A short circuit protection apparatus for a power conversion apparatus supplying power to a load via a plurality of switches connected to each other in parallel includes Ma current detectors each configured to detect a sum of currents flowing through two or more switches among the plurality of switches so as to output a detection signal indicative of the sum that is detected, wherein Ma is 1 less than M, which is the number of the plurality of switches, and a short circuit determiner configured to determine, based on detection signals obtained from the respective Ma current detectors, occurrence of short circuit failure in the plurality of switches to output a cutoff instruction signal for stopping on-off drive of the plurality of switches.

A fault monitoring device may monitor and detect for faults corresponding to a high-side voltage rail, to low-side voltage rail, or internally within a voltage source connected to the high-side voltage rail and the low-side voltage rail. The fault monitoring device may determine sample voltage levels and/or sample resistance values to detect the faults. Also, in various embodiments, the fault monitoring device may perform one or more fault monitoring processes over multiple stages. The fault monitoring device may determine the sample voltage levels and/or the sample resistance values while switching a secondary resistance circuit in different states over the multiple stages.

A fault monitoring device may monitor and detect for faults corresponding to a high-side voltage rail, to low-side voltage rail, or internally within a voltage source connected to the high-side voltage rail and the low-side voltage rail. The fault monitoring device may determine sample voltage levels and/or sample resistance values to detect the faults. Also, in various embodiments, the fault monitoring device may perform one or more fault monitoring processes over multiple stages. The fault monitoring device may determine the sample voltage levels and/or the sample resistance values while switching a secondary resistance circuit in different states over the multiple stages.

A power source combination circuit has a combination circuit and a controller. The combination circuit includes a first power source, a first field-effect transistor, a second power source, and a second field-effect transistor. The controller is configured to control the combination circuit to supply power to a load circuit, obtain a first input voltage, a second input voltage, and a third input voltage, and diagnose, based on the obtained voltages, whether the combination circuit is in a normal state or an abnormal state. The first input voltage is an input side voltage of the first field-effect transistor, the second input voltage is an input side voltage of the second field-effect transistor, and the third input voltage is a voltage at a power source input end of the load circuit.

A power stage includes a control device and a power transistor, the control device comprising a primary circuit comprising: a control module able to generate a control current, a primary circuit malfunction detector able to detect a malfunction, a pulse transformer comprising a primary winding connected to the primary circuit, comprising a secondary winding connected to the secondary circuit, magnetically coupled to the primary winding and able to generate, from the control current, an induced pulse current making it possible to drive the power transistor, a secondary circuit comprising: a power and fault detection controller able to detect a malfunction of the secondary circuit or of the power transistor, the power and fault detection controller being able to communicate the malfunction of the secondary circuit or of the power transistor to the primary circuit malfunction detector.