A transmit receive switch circuit has a first MOSFET (MN1) and a second MOSFET (MN2), goes into a switch-off state at the time of transmission, and goes into a switch-on state at the time of reception. The first MOSFET (MN1) and the second MOSFET (MN2) are connected between an input terminal (SWIN) and an output terminal (SWOUT). The switch circuit includes a shunt circuit (SHNT) that is connected between a common gate (COMG) and a common source (COMS), the common gate being connected to the gates of the first and second MOSFETs, and the common source being connected to the sources of the first and second MOSFETs. When a signal having a negative voltage relative to a reference voltage is applied to the input terminal, a switch that temporarily turns on causes the shunt circuit to short-circuit the common gate and the common source.

Automotive radar systems may employ a reconfigurable connection of antennas to radar transmitters and/or receivers. An illustrative embodiment of an automotive radar system includes: a radar transmitter; a radar receiver; and a digital signal processor coupled to the radar receiver to detect reflections of a signal transmitted by the radar transmitter and to derive signal measurements therefrom. At least one of the radar transmitter and the radar receiver are switchable to provide the digital signal processor with signals from each of multiple combinations of transmit antenna and receive antenna.

Circuitry for an ultrasound device is described. The ultrasound device may include a symmetric switch positioned between a pulser and an ultrasound transducer. The pulser may produce bipolar pulses. The symmetric switch may selectively isolate a receiver from the pulser and the ultrasound transducer during a transmit mode of the device, when the bipolar pulses are provided by the pulser to the ultrasound transducer for transmission, and may selectively permit the receiver to receive signals from the ultrasound transducer during a receive mode. The symmetric switch may be provided with a well switch to remove well capacitances in a signal path of the device.

Aspects of the technology described herein relate to ultrasound device circuitry as may form part of a single substrate ultrasound device having integrated ultrasonic transducers. The ultrasound device circuitry may facilitate the generation of ultrasound waveforms in a manner that is power- and data-efficient.

A diffuse optical tomography (DOT) system for generating a functional image of a lesion region of a subject is described. The DOT system includes a source subsystem configured to generate optical waves, a probe coupled to the source subsystem and configured to emit the optical waves generated by the source subsystem toward the lesion region and to detect optical waves reflected by the lesion region, a detection subsystem configured to convert the optical waves detected by the probe to digital signals, and a computing device including a processor and a memory. The memory includes instructions that program the processor to receive the digital signals sent from the detection subsystem and perform reconstruction using a depth-regularized reconstruction algorithm combined with a semi-automated interactive convolutional neural network (CNN) for depth-dependent reconstruction of absorption distribution.

Aspects of the technology described herein relate to wirelessly offloading, from a wearable ultrasound device, ultrasound data sufficient for forming one or more ultrasound images therefrom. The wearable ultrasound device may include an ultrasound patch. Indications that may be monitored with such a device, and therapeutic uses that may be provided by such a device, are also described. Methods and apparatuses are also described for compounding multilines of ultrasound data on an ultrasound device configured to collect the ultrasound data. Additionally, certain aspects of the technology relate to non-uniform grouping of ultrasound transducers that share a transmit/receive circuit in an ultrasound device.

Aspects of the technology described herein relate to ultrasound device circuitry as may form part of a single substrate ultrasound device having integrated ultrasonic transducers. The ultrasound device circuitry may facilitate the generation of ultrasound waveforms in a manner that is power- and data-efficient.

Aspects of the technology described herein relate to ultrasound device circuitry as may form part of a single substrate ultrasound device having integrated ultrasonic transducers. The ultrasound device circuitry may facilitate the generation of ultrasound waveforms in a manner that is power- and data-efficient.

Aspects of the technology described herein relate to an ultrasound device including a first die that includes an ultrasonic transducer, a first application-specific integrated circuit (ASIC) that is bonded to the first die and includes a pulser, and a second ASIC in communication with the second ASIC that includes integrated digital receive circuitry. In some embodiments, the first ASIC may be bonded to the second ASIC and the second ASIC may include analog processing circuitry and an analog-to-digital converter. In such embodiments, the second ASIC may include a through-silicon via (TSV) facilitating communication between the first ASIC and the second ASIC. In some embodiments, SERDES circuitry facilitates communication between the first ASIC and the second ASIC and the first ASIC includes analog processing circuitry and an analog-to-digital converter. In some embodiments, the technology node of the first ASIC is different from the technology node of the second ASIC.

Aspects of the technology described herein relate to an ultrasound device including a first die that includes an ultrasonic transducer, a first application-specific integrated circuit (ASIC) that is bonded to the first die and includes a pulser, and a second ASIC in communication with the second ASIC that includes integrated digital receive circuitry. In some embodiments, the first ASIC may be bonded to the second ASIC and the second ASIC may include analog processing circuitry and an analog-to-digital converter. In such embodiments, the second ASIC may include a through-silicon via (TSV) facilitating communication between the first ASIC and the second ASIC. In some embodiments, SERDES circuitry facilitates communication between the first ASIC and the second ASIC and the first ASIC includes analog processing circuitry and an analog-to-digital converter. In some embodiments, the technology node of the first ASIC is different from the technology node of the second ASIC.