An optical device (10) includes a first substrate (11) and a second substrate (12) facing each other, a liquid crystal component (13) between the first substrate (11) and the second substrate (12), a first electrode (18) and a second electrode (19) located on the first substrate (11) on the second substrate (12) side, and a first alignment layer (14) that is located on the first substrate (11) on the second substrate (12) side and controls the alignment state of liquid crystal molecules in the liquid crystal component (13), wherein an interface between the liquid crystal component (13) and the first alignment layer (14) forms a non-glide weak anchoring interface (17).

A light distribution control device includes: first upper electrodes and second upper electrodes disposed alternately in a first direction; first lower electrodes and second lower electrodes disposed alternately in a second direction that crosses the first direction; light transmissive regions disposed between an upper electrode set consisting of the first upper electrodes and the second upper electrodes and a lower electrode set consisting of the first lower electrodes and second lower electrodes; and colored electrophoretic particles and a dispersion medium contained in a space between light transmissive regions. Each of the first upper electrodes extends along the space between light transmissive regions. Each of the second upper electrodes extends along a line of light transmissive regions. Each of the first lower electrodes extends along the space between light transmissive regions. Each of the second lower electrodes extends along a line of light transmissive regions.

A driver circuit includes first to third transistors, a first circuit, and a second circuit. In the first transistor, a first terminal is electrically connected to a second wiring, a second terminal is electrically connected to a first wiring, and a gate is electrically connected to the second circuit and a first terminal of the third transistor. In the second transistor, a first terminal is electrically connected to the first wiring, a second terminal is electrically connected to a sixth wiring, a gate is electrically connected to the first circuit and a gate of the third transistor. A second terminal of the third transistor is electrically connected to the sixth wiring. The first circuit is electrically connected to a third wiring, a fourth wiring, a fifth wiring, and the sixth wiring. The second circuit is electrically connected to the first wiring, the second wiring, and the sixth wiring.

Disclosed herein is a tunable diffraction grating using surface acoustic waves. In some embodiments, the tunable diffraction grating includes a piezoelectric substrate including an interdigital transducer (IDT) region and a delay line region; a plurality of IDT electrodes positioned in the IDT region, wherein the IDT electrodes are each individually addressable such that the voltage applied to each of the electrodes is phase shifted, and wherein the IDT electrodes provide the phase shifted voltage to induce surface acoustic waves in the piezoelectric substrate in a pattern which produce a grating in the delay line region. Advantageously, tunable diffraction gratings have many applications including spectrometers for orbiters and rovers to Mars.

A display device includes: a first substrate, including: a gate line having an extension direction; a switch unit electrically connecting to the gate line; a pixel electrode electrically connecting to the switch unit; and a slit in the pixel electrode, wherein a virtual line parallel to the extension direction passes through an end point of the slit which is closest to the gate line, and the pixel electrode is divided into a first portion and a second portion by the virtual line, wherein the first portion is closer to the gate line than the second portion, the first portion and the second portion respectively have a first width and a second width along the extension direction, the first width is a maximum width of the first portion, the second width is a maximum width of the second portion, and the second width is less than the first width.

An array substrate is disclosed. The array substrate includes a semiconductor active layer, a gate insulation layer, a first metal layer, an interlayer dielectric layer, a second metal layer, a planarization layer and a passivation layer sequentially disposed on a base substrate; wherein the array substrate is provided with a row driving unit, including a capacitor structure; wherein the capacitor structure includes a first capacitive plate formed in the semiconductor active layer, a second capacitive plate formed in the first metal layer and a third capacitive plate formed in the second metal layer; and wherein projections of the first capacitive plate and the second capacitive plate on the base substrate are partially overlapped, projections the second capacitive plate and the third capacitive plate on the base substrate are partially overlapped and the third capacitive plate is electrically connected to the first capacitive plate through a first via hole.

A driver circuit includes first to third transistors, a first circuit, and a second circuit. In the first transistor, a first terminal is electrically connected to a second wiring, a second terminal is electrically connected to a first wiring, and a gate is electrically connected to the second circuit and a first terminal of the third transistor. In the second transistor, a first terminal is electrically connected to the first wiring, a second terminal is electrically connected to a sixth wiring, a gate is electrically connected to the first circuit and a gate of the third transistor. A second terminal of the third transistor is electrically connected to the sixth wiring. The first circuit is electrically connected to a third wiring, a fourth wiring, a fifth wiring, and the sixth wiring. The second circuit is electrically connected to the first wiring, the second wiring, and the sixth wiring.

It is an object of the present invention to apply a sufficient electrical field to a liquid crystal material in a horizontal electrical field liquid crystal display device typified by an FFS type. In a horizontal electrical field liquid crystal display, an electrical field is applied to a liquid crystal material right above a common electrode and a pixel electrode using plural pairs of electrodes rather than one pair of electrodes. One pair of electrodes includes a comb-shaped common electrode and a comb-shaped pixel electrode. Another pair of electrodes includes a common electrode provided in a pixel portion and the comb-shaped pixel electrode.

A display device includes: a first substrate including: a switch unit; and a pixel electrode electrically connecting to the switch unit and including: first and second finger portions; a contacting portion electrically connecting to the switch unit through a contact via; a first bending portion between and connecting the first finger portion and the contacting portion, and having a third inner edge; and a second bending portion between and connecting the second finger portion and the contacting portion, and having a fourth inner edge and a second outer edge, wherein the fourth inner edge is between the third inner edge and the second outer edge, a first acute angle included between the third inner edge and a reference line parallel to a first direction substantially parallel to a gate-line-extending direction is greater than a second acute angle included between the second outer edge and the reference line.

A display device and a screen anti-peeping device are provided. The display device includes a display panel and the screen anti-peeping device. The display panel includes at least one bonding area, wherein the bonding area is configured to be coupled to an outer lead. The screen anti-peeping device overlaps with the display panel and includes a plurality of electrode sets, wherein each of the electrode sets includes a first electrode and a second electrode. At least one of the electrode sets is selected to be coupled to at least one control lead, and the selected electrode set is misaligned with the bonding area.