To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.

Provided are a manufacturing method for an array substrate and an array substrate, the method includes: depositing a gate metal layer on a base substrate, and forming a gate electrode by first photolithography process; sequentially depositing a gate insulating layer, a first semiconductor layer, a second semiconductor layer, and a source/drain metal layer, forming an active island, a source electrode, and a drain electrode and forming a channel region between the source electrode and drain electrode by second photolithography process, and converting the second semiconductor layer in channel region into an oxide of silicon; depositing a passivation layer, and forming a conductive via hole on passivation layer over drain electrode by third photolithography process; depositing a transparent conductive layer, and performing fourth photolithography process such that a pixel electrode is formed by transparent conductive layer and that the pixel electrode communicates with the drain electrode through the conductive via hole.

A capacitive electro-optical modulator includes a silicon layer, a germanium or silicon-germanium strip overlying the silicon layer, and a silicon strip overlying the germanium or silicon-germanium strip. The silicon strip is wider than the germanium or silicon-germanium strip. An insulator is laterally adjacent the germanium or silicon-germanium strip and the silicon strip and has an upper surface that is flush with an upper surface of the silicon strip. An insulating layer overlies the insulator and the silicon strip. A layer of III-V material overlies the insulating layer. The layer of III-V material is formed as a third strip arranged facing the silicon strip and separated therefrom by a portion of the insulating layer.

By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.

In an example, a display device comprises a substrate with pixels arranged in a display portion, a signal line control circuit connected to signal lines, a plurality of thin film transistors inputting a pixel signal to a corresponding one of the pixels from the corresponding one of the signal lines, a common electrode overlapping the entire display portion, an insulating film disposed on the common electrode, a common line connected to the common electrode through contact holes in the insulating film, where the common line is disposed between the substrate and the insulating film, and outside the display portion along four sides of the display portion, a plurality of gate lines electrically connected to the thin film transistors, and a gate line control circuit connected to and configured to provide a gate signal to each of the gate lines, and disposed between the display portion and the common line.

A display device that is suitable for increasing its size is provided.

The display device includes first to third wirings, a first transistor, first to third conductive layers, and a first pixel electrode; the first wiring extends in a first direction and intersects with the second and the third wirings; the second and the third wirings each extend in a second direction intersecting with the first direction; a gate of the first transistor is electrically connected to the first wiring; one of a source and a drain of the first transistor is electrically connected to the second wiring through the first to the third conductive layers; the second conductive layer includes a region overlapping with the third wiring; the first conductive layer, the third conductive layer, and the first pixel electrode contain the same material; the first wiring and the second conductive layer contain the same material; the first wiring is supplied with a selection signal; and the second and the third wirings are supplied with different signals.

A manufacturing method of a TFT array substrate is provided, comprising: depositing and forming a gate and a gate scanning line; depositing sequentially a gate insulating layer, an active layer and a second metal layer; depositing and forming a first photoresist layer and a second photoresist layer on the second metal layer; first photoresist layer comprising a first-stage photoresist layer, second-stage photoresist layer and third-stage photoresist layer with increasing thickness, the first-stage photoresist layer being in the middle of the first photoresist layer and a channel being formed; ashing to remove first-stage photoresist layer, forming a source and a drain by etching; and ashing to remove the second-stage photoresist layer, and then depositing a passivation layer as a whole; stripping third-stage photoresist layer and second photoresist layer, depositing and forming a pixel electrode and a common electrode.

A novel and highly convenient or reliable display panel is provided which includes a first driver circuit, a second driver circuit, a first scan line, a second scan line, and a first signal line. The first driver circuit supplies a selection signal. The second driver circuit supplies a predetermined voltage, first data using a voltage greater than or equal to the predetermined voltage, and second data using a voltage less than or equal to the predetermined voltage. The first scan line is selected in a first period. The second scan line adjacent to the first scan line is selected in a third period. The first signal line receives the first data in the first period, the predetermined voltage in a second period, and the second data in the third period. The second period is provided between the first period and the third period.

A thin film transistor according to an embodiment of the present invention includes: a gate electrode supported by a substrate; a gate insulating layer covering the gate electrode; a silicon semiconductor layer being provided on the gate insulating layer and having a crystalline silicon region, the crystalline silicon region including a first region, a second region, and a channel region located between the first region and the second region, such that the channel region, the first region, and the second region overlap the gate electrode via the gate insulating layer; an insulating protection layer disposed on the silicon semiconductor layer so as to cover the channel region and allow the first region and the second region to be exposed; a source electrode electrically connected to the first region; and a drain electrode electrically connected to the second region. The channel region is lower in crystallinity than the first region and the second region.

Systems and methods are described herein for an optical beam-steering device that includes an optical transmitter and/or receiver to transmit and/or receive optical radiation from an optically reflective surface. An array of adjustable dielectric resonator elements is arranged on the surface with inter-element spacings less than an optical operating wavelength. A controller applies a pattern of voltage differentials to the adjustable dielectric resonator elements. The pattern of voltage differentials corresponds to a sub-wavelength reflection phase pattern for reflecting the optical electromagnetic radiation. One embodiment of a dielectric resonator element includes first and second dielectric members extending from the surface. The dielectric resonator elements are spaced from one another to form a gap or channel therebetween. A voltage-controlled adjustable refractive index material is disposed within the gap.