A photolithography method is provided. The photolithography method includes forming a photoresist layer on a wafer, exposing a portion of the photoresist layer by using an exposure device and a mask, and forming a photoresist pattern by removing a non-exposed portion of the photoresist layer. The mask includes a substrate having a main pattern area and a blocking area outside the main pattern area, a main pattern on the main pattern area of the substrate, and a blocking pattern on the blocking area of the substrate. An external circumference of the blocking pattern extends to the maximum area of the mask that may be illuminated by the exposure device or to the outside of the maximum area of the mask.

The present disclosure provides a mask pattern for a semiconductor photolithography process and a semiconductor photolithography process. The mask pattern comprises: a pattern, the pattern comprising a light-transmitting area and a light-shielding area which are alternately arranged, the pattern having a boundary formed by an end portion of the light-transmitting area and an end portion of the light-shielding area, and an edge light-transmitting area being formed at the boundary. By the mask pattern of the present disclosure, a pattern with smooth edges can be formed on a wafer, and the edge roughness of the pattern is low, which meets the design requirements, thereby improving product quality and yield.

The present disclosure provides a mask pattern for a semiconductor photolithography process and a semiconductor photolithography process. The mask pattern comprises: a pattern, the pattern comprising a light-transmitting area and a light-shielding area which are alternately arranged, the pattern having a boundary formed by an end portion of the light-transmitting area and an end portion of the light-shielding area, and an edge light-transmitting area being formed at the boundary. By the mask pattern of the present disclosure, a pattern with smooth edges can be formed on a wafer, and the edge roughness of the pattern is low, which meets the design requirements, thereby improving product quality and yield.

A method of forming an imprint template. A hard mask layer is formed at a first side first side of a template plate. An imprint lithography is performed to form a patterned hard mask covering the first region, the patterned hard mask having a pattern portion and an edge portion defined in the same imprint lithography. The template plate is dry etched with the first region of the template plate covered with the patterned hard mask. An additional mask layer is formed on the patterned hard mask. A wet etch process is performed with both the patterned hard mask and the additional mask layer formed on the template plate to form a mesa under the pattern portion with the edge portion of the hard mask overhanging on the second region of the template plate.

A method of forming an imprint template. A hard mask layer is formed at a first side first side of a template plate. An imprint lithography is performed to form a patterned hard mask covering the first region, the patterned hard mask having a pattern portion and an edge portion defined in the same imprint lithography. The template plate is dry etched with the first region of the template plate covered with the patterned hard mask. An additional mask layer is formed on the patterned hard mask. A wet etch process is performed with both the patterned hard mask and the additional mask layer formed on the template plate to form a mesa under the pattern portion with the edge portion of the hard mask overhanging on the second region of the template plate.

Embodiments described herein may be related to apparatuses, processes, and techniques related to using full stack overlay cell (FSOL) targets within lithography masks and on fabricated layers of a substrate in order to align or to assess the alignment of fabricated layers of the substrate during the substrate manufacturing process. Other embodiments may be described and/or claimed.

A method for semiconductor metrology includes depositing a first film layer on a semiconductor substrate and a second film layer overlying the first film layer. The first and second film layers are patterned to create an overlay target having a specified geometrical form by using a projection system having a predefined resolution limit to project optical radiation onto the semiconductor substrate through at least one mask. The mask contains target features having target feature dimensions no less than the predefined resolution limit in an arrangement corresponding to the specified geometrical form of the overlay target and assist features interleaved with the target features and having at least one assist feature dimension that is less than the predefined resolution limit.

A method for semiconductor metrology includes depositing a first film layer on a semiconductor substrate and a second film layer overlying the first film layer. The first and second film layers are patterned to create an overlay target having a specified geometrical form by using a projection system having a predefined resolution limit to project optical radiation onto the semiconductor substrate through at least one mask. The mask contains target features having target feature dimensions no less than the predefined resolution limit in an arrangement corresponding to the specified geometrical form of the overlay target and assist features interleaved with the target features and having at least one assist feature dimension that is less than the predefined resolution limit.

A method may include forming a first grating and a second grating, disposed in a region of vertical overlap of the first and second gratings on different levels, respectively, having substantially the same pitch, and inclined with respect to each other, such that a bias value between the first and second gratings is changed along a length direction of the first and second gratings, using a lithography process. A method may include emitting a beam to the first and second gratings; and obtaining trend information associated with a diffracted beam from an image pattern of a beam from the first and second gratings, using the emitted beam, in which the trend information may concern changes in the intensity of the diffracted beam according to the bias value. An overlay error in at least one grating may be determined based on the trend information and an intensity of a diffracted beam.

A method may include forming a first grating and a second grating, disposed in a region of vertical overlap of the first and second gratings on different levels, respectively, having substantially the same pitch, and inclined with respect to each other, such that a bias value between the first and second gratings is changed along a length direction of the first and second gratings, using a lithography process. A method may include emitting a beam to the first and second gratings; and obtaining trend information associated with a diffracted beam from an image pattern of a beam from the first and second gratings, using the emitted beam, in which the trend information may concern changes in the intensity of the diffracted beam according to the bias value. An overlay error in at least one grating may be determined based on the trend information and an intensity of a diffracted beam.