A method of manufacturing a reticle includes depositing an etch stop layer over a substrate; and depositing an absorber layer over the etch stop layer. The method further includes depositing a hard mask layer over the absorber layer, wherein the hard mask layer includes tantalum. The method includes patterning the hard mask layer. The method further includes performing a first etch process to remove a portion of the absorber layer underneath the patterned hard mask. The method includes performing a second etch process to partially remove a portion of a thickness of an etch stop layer underneath the removed portion of the absorber layer, wherein performing the third etch process comprises maintaining a remaining thickness of the etch stop layer underneath the removed portion of the absorber. The method further includes maintaining the remaining thickness of the etch stop layer through a termination of the method of manufacturing the reticle.

A method includes depositing a first work function layer over a gate dielectric layer, forming a first hard mask layer over the first work function layer, forming a photoresist mask over the first hard mask layer, where forming the photoresist mask includes depositing a bottom anti-reflective coating (BARC) layer over the first hard mask layer, etching a portion of the BARC layer, etching a portion of the first hard mask layer using the BARC layer as a mask, etching a portion of the first work function layer to expose a portion of the gate dielectric layer through the first hard mask layer and the first work function layer, removing the first hard mask layer, and depositing a second work function layer over the first work function layer and over the portion of the gate dielectric layer.

A method includes depositing a first work function layer over a gate dielectric layer, forming a first hard mask layer over the first work function layer, forming a photoresist mask over the first hard mask layer, where forming the photoresist mask includes depositing a bottom anti-reflective coating (BARC) layer over the first hard mask layer, etching a portion of the BARC layer, etching a portion of the first hard mask layer using the BARC layer as a mask, etching a portion of the first work function layer to expose a portion of the gate dielectric layer through the first hard mask layer and the first work function layer, removing the first hard mask layer, and depositing a second work function layer over the first work function layer and over the portion of the gate dielectric layer.

The present invention provides a fluid purging system (100) for an optical element (120), comprising a fluid guiding unit arranged to guide a fluid, provided by a fluid supply system, over at least a curved portion of an optical surface (122) of the optical element. The fluid guiding unit comprises a fluid inlet and a first nozzle unit (110) for providing a fluid to the optical surface. The fluid guiding unit being formed by at least a first wall portion (102) and at least a second wall portion (104), wherein the second wall portion being configured to face the optical surface and to follow a contour of the optical surface. The second wall portion comprises a second nozzle unit (112).

The present invention provides a fluid purging system (100) for an optical element (120), comprising a fluid guiding unit arranged to guide a fluid, provided by a fluid supply system, over at least a curved portion of an optical surface (122) of the optical element. The fluid guiding unit comprises a fluid inlet and a first nozzle unit (110) for providing a fluid to the optical surface. The fluid guiding unit being formed by at least a first wall portion (102) and at least a second wall portion (104), wherein the second wall portion being configured to face the optical surface and to follow a contour of the optical surface. The second wall portion comprises a second nozzle unit (112).

An extreme ultraviolet (EUV) mask includes a multilayer Mo/Si stack comprising alternating Mo and Si layers disposed over a first major surface of a mask substrate, a capping layer made of ruthenium (Ru) disposed over the multilayer Mo/Si stack, and an absorber layer on the capping layer. The EUV mask includes a circuit pattern area and a particle attractive area, and the capping layer is exposed at bottoms of patterns in the particle attractive area.

An extreme ultraviolet (EUV) mask includes a multilayer Mo/Si stack comprising alternating Mo and Si layers disposed over a first major surface of a mask substrate, a capping layer made of ruthenium (Ru) disposed over the multilayer Mo/Si stack, and an absorber layer on the capping layer. The EUV mask includes a circuit pattern area and a particle attractive area, and the capping layer is exposed at bottoms of patterns in the particle attractive area.

A reflection mode photomask includes a multilayer over a substrate. The reflection mode photomask further includes a plurality of absorber stacks over the multilayer. Each absorber stack of the plurality of absorber stacks includes an absorber layer, wherein a material of the absorber layer is selected from the group consisting of tantalum oxynitride and tantalum silicon oxynitride. Each absorber stack of the plurality of absorber stacks further includes an anti-reflective coating (ARC) layer on the absorber layer, wherein a material of the ARC layer is selected from the group consisting of tantalum nitride and tantalum silicon.

A reflection mode photomask includes a multilayer over a substrate. The reflection mode photomask further includes a plurality of absorber stacks over the multilayer. Each absorber stack of the plurality of absorber stacks includes an absorber layer, wherein a material of the absorber layer is selected from the group consisting of tantalum oxynitride and tantalum silicon oxynitride. Each absorber stack of the plurality of absorber stacks further includes an anti-reflective coating (ARC) layer on the absorber layer, wherein a material of the ARC layer is selected from the group consisting of tantalum nitride and tantalum silicon.

An extreme ultraviolet (EUV) mask includes a multilayer Mo/Si stack comprising alternating Mo and Si layers disposed over a first major surface of a mask substrate, a capping layer made of ruthenium (Ru) disposed over the multilayer Mo/Si stack, and an absorber layer on the capping layer. The EUV mask includes a circuit pattern area and a particle attractive area, and the capping layer is exposed at bottoms of patterns in the particle attractive area.