An integrated device product having objects positioned in accordance with in-situ constraints. Said in-situ constraints comprise predetermined constraints and their local modifications. These local modifications, individually formulated for a specific pair of objects, account for on-the-spot conditions that influence the optimal positioning of the objects. The present invention improves the yield of integrated devices by adding local process modification distances to the predetermined constraints around processing hotspots thus adding extra safety margin to the device yield.

A method includes determining topographic information of a substrate for use in a lithographic imaging system, determining or estimating, based on the topographic information, imaging error information for a plurality of points in an image field of the lithographic imaging system, adapting a design for a patterning device based on the imaging error information. In an embodiment, a plurality of locations for metrology targets is optimized based on imaging error information for a plurality of points in an image field of a lithographic imaging system, wherein the optimizing involves minimizing a cost function that describes the imaging error information. In an embodiment, locations are weighted based on differences in imaging requirements across the image field.

A method includes determining topographic information of a substrate for use in a lithographic imaging system, determining or estimating, based on the topographic information, imaging error information for a plurality of points in an image field of the lithographic imaging system, adapting a design for a patterning device based on the imaging error information. In an embodiment, a plurality of locations for metrology targets is optimized based on imaging error information for a plurality of points in an image field of a lithographic imaging system, wherein the optimizing involves minimizing a cost function that describes the imaging error information. In an embodiment, locations are weighted based on differences in imaging requirements across the image field.

A semiconductor device includes a first and a second power rails extending in a row direction, a third power rail extending in the row direction between the first and second power rail, and a first cell arranged between the first second power rails. A cell height of the first cell in a column direction perpendicular to the row direction is equal to a pitch between the first and second power rails. The semiconductor device also includes a second cell arranged between the first and third power rails. A cell height of the second cell in the column direction is equal to a pitch between the first and third power rails. A first active region of the first cell includes a first width in the column direction greater than a second width, in the column direction, of a second active region in the second cell.

A semiconductor device includes a first and a second power rails extending in a row direction, a third power rail extending in the row direction between the first and second power rail, and a first cell arranged between the first second power rails. A cell height of the first cell in a column direction perpendicular to the row direction is equal to a pitch between the first and second power rails. The semiconductor device also includes a second cell arranged between the first and third power rails. A cell height of the second cell in the column direction is equal to a pitch between the first and third power rails. A first active region of the first cell includes a first width in the column direction greater than a second width, in the column direction, of a second active region in the second cell.

Disclosed are methods of advanced process control (APC) for particular processes. A particular process (e.g., a photolithography or etch process) is performed on a wafer to create a pattern of features. A parameter is measured on a target feature and the value of the parameter is used for APC. However, instead of performing APC based directly on the actual parameter value, APC is performed based on an adjusted parameter value. Specifically, an offset amount (which is previously determined based on an average of a distribution of parameter values across all of the features) is applied to the actual parameter value to acquire an adjusted parameter value, which better represents the majority of features in the pattern. Performing this APC method minimizes dimension variations from pattern to pattern each time the same pattern is generated on another region of the same wafer or on a different wafer using the particular process.

Disclosed are methods of advanced process control (APC) for particular processes. A particular process (e.g., a photolithography or etch process) is performed on a wafer to create a pattern of features. A parameter is measured on a target feature and the value of the parameter is used for APC. However, instead of performing APC based directly on the actual parameter value, APC is performed based on an adjusted parameter value. Specifically, an offset amount (which is previously determined based on an average of a distribution of parameter values across all of the features) is applied to the actual parameter value to acquire an adjusted parameter value, which better represents the majority of features in the pattern. Performing this APC method minimizes dimension variations from pattern to pattern each time the same pattern is generated on another region of the same wafer or on a different wafer using the particular process.

A memory device including: active regions; gate electrodes which are substantially aligned relative to four corresponding track lines such that the memory device has a width of four contacted poly pitch (4 CPP) and are electrically coupled to the active regions; contact-to-transistor-component structures (MD structures) which are electrically coupled to the active regions, and are interspersed among corresponding ones of the gate electrodes; via-to-gate/MD (VGD) structures which are electrically coupled to the gate electrodes and the MD structures; conductive segments which are in a first layer of metallization (M_1st layer), and are electrically coupled to the VGD structures; buried contact-to-transistor-component structures (BVD structures) which are electrically coupled to the active regions; and buried conductive segments which are in a first buried layer of metallization (BM_1st layer), and are electrically coupled to the BVD structures, and correspondingly provide a first reference voltage or a second reference voltage.

A method performed by a computing system includes receiving a layout pattern, receiving a target pattern associated with the layout pattern, receiving a set of constraints related to the target pattern, simulating a first contour associated with the layout pattern, determining a first difference between the first contour and the target pattern, simulating a second contour associated with a modified layout pattern, and determining a second difference between the second contour and a modified target pattern. The modified target pattern is different than the target pattern and within the constraints. The method further includes fabricating a mask having the final layout pattern.

A method performed by a computing system includes receiving a layout pattern, receiving a target pattern associated with the layout pattern, receiving a set of constraints related to the target pattern, simulating a first contour associated with the layout pattern, determining a first difference between the first contour and the target pattern, simulating a second contour associated with a modified layout pattern, and determining a second difference between the second contour and a modified target pattern. The modified target pattern is different than the target pattern and within the constraints. The method further includes fabricating a mask having the final layout pattern.