Initial source shapes for source mask optimization are determined based on a layout of the lithographic mask. In one approach, a layout of a lithographic mask is received. Different sections of the lithographic mask, referred to as clips, are selected. These clips are applied to a machine learning model which infers source shapes from the clips. The inferred source shapes are used as the initial source shapes for source mask optimization.

A method for manufacturing a semiconductor device, includes receiving a first layout including patterns for the manufacturing of the semiconductor device, generating a second layout by performing machine learning-based process proximity correction (PPC) based on features of the patterns of the first layout, generating a third layout by performing optical proximity correction (OPC) on the second layout, and performing a multiple patterning process based on the third layout. The multiple patterning process includes patterning first-type patterns, and patterning second-type patterns. The machine learning-based process proximity correction is performed based on features of the first-type patterns and features of the second-type patterns.

A pattern decomposition method including following steps is provided. A target pattern is provided, wherein the target pattern includes first patterns and second patterns alternately arranged, and the width of the second pattern is greater than the width of the first pattern. Each of the second patterns is decomposed into a third pattern and a fourth pattern, wherein the third pattern and the fourth pattern have an overlapping portion, and a pattern formed by overlapping the third pattern and the fourth pattern is the same as the second pattern. The third patterns and the first pattern adjacent to the fourth pattern are designated as first photomask patterns of a first photomask. The fourth patterns and the first pattern adjacent to the third pattern are designated as second photomask patterns of a second photomask.

A pattern decomposition method including following steps is provided. A target pattern is provided, wherein the target pattern includes first patterns and second patterns alternately arranged, and the width of the second pattern is greater than the width of the first pattern. Each of the second patterns is decomposed into a third pattern and a fourth pattern, wherein the third pattern and the fourth pattern have an overlapping portion, and a pattern formed by overlapping the third pattern and the fourth pattern is the same as the second pattern. The third patterns and the first pattern adjacent to the fourth pattern are designated as first photomask patterns of a first photomask. The fourth patterns and the first pattern adjacent to the third pattern are designated as second photomask patterns of a second photomask.

The present application relates to a dispatch method for a production line in a semiconductor process, a storage medium and a semiconductor device. The dispatch method for a production line in a semiconductor process can acquire an overlay error reference curve of a product lot to be exposed in equipment and set an overlay error range according to the overlay error reference curve. At the end of exposure, an overlay error for the product lot to be exposed can be acquired, and it can be determined whether the overlay error falls into the overlay error range. If the overlay error for the product lot to be exposed does not fall into the overlay error range, the product lot to be exposed can be continuously machined by this equipment.

The present application relates to a dispatch method for a production line in a semiconductor process, a storage medium and a semiconductor device. The dispatch method for a production line in a semiconductor process can acquire an overlay error reference curve of a product lot to be exposed in equipment and set an overlay error range according to the overlay error reference curve. At the end of exposure, an overlay error for the product lot to be exposed can be acquired, and it can be determined whether the overlay error falls into the overlay error range. If the overlay error for the product lot to be exposed does not fall into the overlay error range, the product lot to be exposed can be continuously machined by this equipment.

A chip design methodology and a set of integrated circuits that are taped out from a common design database are disclosed. The area of a full instance of the integrated circuit is defined, and one or more chop lines are defined to identify portions that will be removed for one or more partial instances. A variety of techniques and mechanisms are defined to permit the tape outs to occur from a common design database, so that the effort to tape out partial instances may be minimized beyond that to tape out the full instance.

A chip design methodology and a set of integrated circuits that are taped out from a common design database are disclosed. The area of a full instance of the integrated circuit is defined, and one or more chop lines are defined to identify portions that will be removed for one or more partial instances. A variety of techniques and mechanisms are defined to permit the tape outs to occur from a common design database, so that the effort to tape out partial instances may be minimized beyond that to tape out the full instance.

Computer-implemented systems and methods for automatically eliminating connectivity mismatches in a mask layout block are provided. The disclosed systems and methods maintain the process design rules (DRC Clean), connectivity (LVS Clean) correctness, and obey Reliability Verification (RV) and DFM (Design for Manufacturability) constraints. Disclosed systems and methods analyze a physical connection of a selected polygon or net in a mask layout block and obtain connectivity information associated with the selected polygon or net from a netlist or external constraints file. The physical connection of the selected polygon or net is compared with the obtained connectivity information to determine whether there is a connectivity mismatch associated with the selected polygon or net. If there is a determined connectivity mismatch, a violation marker representing the connectivity mismatch is generated and the connectivity mismatch is corrected by placing, moving, or editing the selected polygon or net to modify the physical connection.

A method to improve a lithographic process for imaging a portion of a patterning device pattern onto a substrate using a lithographic projection having an illumination system and projection optics, the method including: (1) obtaining a simulation model that models projection of radiation by the projection optics, wherein the simulation model models an effect of an obscuration in the projection optics, and configuring, based on the model, the portion of the patterning device pattern, and/or (2) obtaining a simulation model that models projection of radiation by the projection optics, wherein the simulation model models an anamorphic demagnification of radiation by the projection optics, and configuring, based on the model, the portion of the patterning device pattern taking into account an anamorphic manufacturing rule or anamorphic manufacturing rule ratio.