Various aspects of the present disclosed technology relate to techniques for inverse-lithography-technology-based optical proximity correction. A layout design is received. A machine learning-based clustering process is then performed to separate layout features in the layout design into groups of layout features. For layout features in each of the groups of layout features, preliminary corrections are determined. The determination may be based on inverse lithography technology. The preliminary corrections are applied to the layout design to generate a pre-processed layout design. An inverse lithography technology process is performed on the pre-processed layout design to generate a processed layout design. Masks can be manufactured based on the processed layout design.

Various aspects of the present disclosed technology relate to techniques for inverse-lithography-technology-based optical proximity correction. A layout design is received. A machine learning-based clustering process is then performed to separate layout features in the layout design into groups of layout features. For layout features in each of the groups of layout features, preliminary corrections are determined. The determination may be based on inverse lithography technology. The preliminary corrections are applied to the layout design to generate a pre-processed layout design. An inverse lithography technology process is performed on the pre-processed layout design to generate a processed layout design. Masks can be manufactured based on the processed layout design.

Methods for reticle enhancement technology (RET) for use with variable shaped beam (VSB) lithography include inputting a desired pattern to be formed on a substrate; determining an initial mask pattern from the desired pattern for the substrate; optimizing the initial mask pattern for wafer quality using a VSB exposure system; and outputting the optimized mask pattern. Methods for fracturing a pattern to be exposed on a surface using VSB lithography include inputting an initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by the union of the initial pattern with locations on the grid; merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots.

Methods for reticle enhancement technology (RET) for use with variable shaped beam (VSB) lithography include inputting a desired pattern to be formed on a substrate; determining an initial mask pattern from the desired pattern for the substrate; optimizing the initial mask pattern for wafer quality using a VSB exposure system; and outputting the optimized mask pattern. Methods for fracturing a pattern to be exposed on a surface using VSB lithography include inputting an initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by the union of the initial pattern with locations on the grid; merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots.

A memory device includes a bit line, a word line, a memory cell including a capacitor and a transistor, and a controller. The transistor has a gate terminal coupled to the word line, a first terminal, and a second terminal. The capacitor has a first end coupled to the first terminal of the transistor, a second end coupled to the bit line, and an insulating material between the first end and the second end. The controller, in a programming operation, applies a turn-ON voltage via the word line to the gate terminal of the transistor to turn ON the transistor, and applies a program voltage via the bit line to the second end of the capacitor to apply, while the transistor is turned ON, a predetermined break-down voltage or higher between the first end and the second end of the capacitor to break down the insulating material of the capacitor.

A memory device includes a bit line, a word line, a memory cell including a capacitor and a transistor, and a controller. The transistor has a gate terminal coupled to the word line, a first terminal, and a second terminal. The capacitor has a first end coupled to the first terminal of the transistor, a second end coupled to the bit line, and an insulating material between the first end and the second end. The controller, in a programming operation, applies a turn-ON voltage via the word line to the gate terminal of the transistor to turn ON the transistor, and applies a program voltage via the bit line to the second end of the capacitor to apply, while the transistor is turned ON, a predetermined break-down voltage or higher between the first end and the second end of the capacitor to break down the insulating material of the capacitor.

To increase the efficiency of electronic design automation, employ a first subset of integrated circuit patterning modeling data to generate weights of a neural network-based patterning model; employ a second subset of integrated circuit patterning modeling data to generate updated weights of the neural network-based patterning model, to obtain an updated neural network-based patterning model; evaluate the updated neural network-based patterning model; and responsive to the evaluating of the updated neural network-based patterning model being successfully completed, deploy the updated neural network-based patterning model.

The present invention provides a processing system that includes a first apparatus and a second apparatus, and processes a substrate, wherein the first apparatus includes a first measurement unit configured to detect a first structure and a second structure different from the first structure provided on the substrate, and measure a relative position between the first structure and the second structure, and the second apparatus includes an obtainment unit configured to obtain the relative position measured by the first measurement unit, a second measurement unit configured to detect the second structure and measure a position of the second structure, and a control unit configured to obtain a position of the first structure based on the relative position obtained by the obtainment unit and the position of the second structure measured by the second measurement unit.

A layout geometry of a lithographic mask is received. The layout geometry includes at least one shape having one or more rounded corners. The layout geometry is partitioned into a plurality of feature images, for example as selected from a library. The feature images include at least one mask corner rounding (MCR)-corrected feature image that accounts for the rounded corners of the shape. The feature images have corresponding mask 3D (M3D) filters, which represent the electromagnetic scattering effect of that feature image for a given source illumination. The mask function contribution from each of the feature images is calculated by convolving the feature image with its corresponding M3D filter. The mask function contributions are combined to determine a mask function for the mask illuminated by the source illumination.

A layout geometry of a lithographic mask is received. The layout geometry includes at least one shape having one or more rounded corners. The layout geometry is partitioned into a plurality of feature images, for example as selected from a library. The feature images include at least one mask corner rounding (MCR)-corrected feature image that accounts for the rounded corners of the shape. The feature images have corresponding mask 3D (M3D) filters, which represent the electromagnetic scattering effect of that feature image for a given source illumination. The mask function contribution from each of the feature images is calculated by convolving the feature image with its corresponding M3D filter. The mask function contributions are combined to determine a mask function for the mask illuminated by the source illumination.