A method and apparatus for forming a resist pattern may be provided. In the method for forming a resist pattern, a resist layer may be formed on a base layer, an electric field may be applied to the resist layer in a thickness direction of the resist layer, and a portion of the resist layer may be exposed with extreme ultraviolet (EUV) light while applying the electric field. A lithography apparatus for performing the method of forming a resist pattern may include at least an exposure part and an electric field forming part. The exposure part may be configured to expose a portion of the resist layer with extreme ultraviolet (EUV) light. The electric field forming part may be configured to apply an electric field to the resist layer.

A method for correcting misalignments is provided. An alignment for each device of a group of devices mounted on a substrate is determined. An alignment error for the group of devices mounted on the substrate is determined based on the respective alignment for each device. One or more correction factors are calculated based on the alignment error. The alignment error is corrected based on the one or more correction factors.

A projection exposure apparatus (10) includes a mask mark illumination light source (21) capable of irradiating a mask mark (MM) with exposure light itself or a first alignment light (L1) having substantially the same wavelength as the exposure light, and an alignment unit (30) having a work mark illumination light source (31) capable of irradiating a work mark (WM) with second alignment light (L2) having a wavelength different from the wavelength of the exposure light, an imaging device (32), and an imaging optical system (40). The imaging optical system (40) includes a first dichroic prism (41) for synthesizing the first alignment light (L1) and the light from the work mark (WM) and emitting the synthesized light toward the imaging device (32), and an optical path length changing optical system (42) for splitting and merging the first alignment light (L1), in which the optical positional relationships of the work mark (WM) and the image (MMI) of the mask mark (MM) with respect to the imaging device (32) are equivalent. Accordingly, it is possible to provide a projection exposure apparatus and a projection exposure method that allow high-precision alignment even in a small-sized exposure area.

A method of fabricating a circuit element, such as a quantum computing circuit element, including obtaining a lithography mask write file that includes mask information characterizing one or more mask features, obtaining a uniformity function that is configured to modify the mask information to compensate for a non-uniform deposition process, applying the uniformity function to the lithography mask write to obtain a modified lithography mask write file, and performing lithography as directed by the modified lithography mask write file.

A method and apparatus for forming a resist pattern may be provided. In the method for forming a resist pattern, a resist layer may be formed on a base layer, an electric field may be applied to the resist layer in a thickness direction of the resist layer, and a portion of the resist layer may be exposed with extreme ultraviolet (EUV) light while applying the electric field. A lithography apparatus for performing the method of forming a resist pattern may include at least an exposure part and an electric field forming part. The exposure part may be configured to expose a portion of the resist layer with extreme ultraviolet (EUV) light. The electric field forming part may be configured to apply an electric field to the resist layer.

Semiconductor processing apparatuses and methods are provided in which a semiconductor wafer is flipped and then rotated between patterning of front and back sides of the semiconductor wafer by first and second reticles, respectively. In some embodiments, a method includes patterning, by a first reticle, a first layer on a first side of a semiconductor wafer while the first side of the semiconductor wafer is facing a first direction. The semiconductor wafer is then flipped. A second side of the semiconductor wafer that is opposite the first side faces the first direction after the flipping the semiconductor wafer. The semiconductor wafer is then rotated about a rotational axis extending along the first direction, and a second layer on the second side of the semiconductor wafer is patterned by a second reticle.

Semiconductor processing apparatuses and methods are provided in which a semiconductor wafer is flipped and then rotated between patterning of front and back sides of the semiconductor wafer by first and second reticles, respectively. In some embodiments, a method includes patterning, by a first reticle, a first layer on a first side of a semiconductor wafer while the first side of the semiconductor wafer is facing a first direction. The semiconductor wafer is then flipped. A second side of the semiconductor wafer that is opposite the first side faces the first direction after the flipping the semiconductor wafer. The semiconductor wafer is then rotated about a rotational axis extending along the first direction, and a second layer on the second side of the semiconductor wafer is patterned by a second reticle.

A semiconductor manufacturing system includes a calculation unit that calculates an inclination degree of an incidence direction of an etchant in an etching device according to a worn state of a part of the etching device. A correction unit corrects a second exposure pattern so that an edge position in the second exposure pattern including an edge is shifted from a first exposure pattern according to the calculated inclination degree. An exposure device exposes a second resist film formed on the substrate from which a first resist pattern is removed with the second exposure pattern. A development device develops the second resist film and forms a second resist pattern on the substrate. The etching device performs etching processing on the substrate by using the second resist pattern as a mask.

A method for correcting misalignments is provided. An alignment for each device of a group of devices mounted on a substrate is determined. An alignment error for the group of devices mounted on the substrate is determined based on the respective alignment for each device. One or more correction factors are calculated based on the alignment error. The alignment error is corrected based on the one or more correction factors.

A processing method in one embodiment includes: a step that takes an image of the end face of a reference substrate, whose warp amount is known, over the whole periphery thereof using a camera to obtain shape data of the end face of the reference substrate; a step that takes an image of the end face of a substrate over the whole periphery thereof using a camera to obtain shape data of the end face of the substrate; a step that calculates warp amount of the substrate based on the obtained shape data; a step that forms a resist film on a surface of the substrate; a step that determines the supply position from which an organic solvent is to be supplied to a peripheral portion of the resist film and dissolves the peripheral portion by the solvent supplied from the supply position to remove the same from the substrate.