A measurement apparatus and method for determining a substrate grid describing a deformation of a substrate prior to exposure of the substrate in a lithographic apparatus configured to fabricate one or more features on the substrate. Position data for a plurality of first features and/or a plurality of second features on the substrate is obtained. Asymmetry data for at least a feature of the plurality of first features and/or the plurality of second features is obtained. The substrate grid based on the position data and the asymmetry data is determined. The substrate grid and asymmetry data are passed to the lithographic apparatus for controlling at least part of an exposure process to fabricate one or more features on the substrate.

In a lithographic apparatus, a localized area of the substrate surface under a projection system is immersed in liquid. The height of a liquid supply system above the surface of the substrate can be varied using actuators. A control system uses feedforward or feedback control with input of the surface height of the substrate to maintain the liquid supply system at a predetermined height above the surface of the substrate.

A method for inspecting a spatial light modulator includes: performing such control that in an inspection target area in an array of mirror elements, the mirror elements in a first state in which incident light is given a phase change amount of 0 and the mirror elements in a second state in which incident light is given a phase change amount of 180 () become arrayed in a checkered pattern; guiding light having passed the inspection target area to a projection optical system with a resolution limit coarser than a width of an image of one mirror element, to form a spatial image; and inspecting a characteristic of the spatial light modulator from the spatial image. This method allows us to readily perform the inspection of the characteristic of the spatial light modulator having the array of optical elements.

Disclosed herein are several methods of reducing one or more pattern displacement errors, contrast loss, best focus shift , tilt of a Bossung curve of a portion of a design layout used in a lithographic process for imaging that portion onto a substrate using a lithographic apparatus. The methods include adjusting an illumination source of the lithographic apparatus, placing assist features onto or adjusting positions and/or shapes existing assist features in the portion. Adjusting the illumination source and/or the assist features may be by an optimization algorithm.

A processing method in one embodiment includes: a step that takes an image of the end face of a reference substrate, whose warp amount is known, over the whole periphery thereof using a camera to obtain shape data of the end face of the reference substrate over the whole periphery of the reference substrate; a step that takes an image of the end face of a substrate over the whole periphery thereof using a camera to obtain shape data of the end face of the substrate over the whole periphery of the substrate; a step that calculates warp amount of the substrate based on the obtained shape data; a step that forms a resist film on a surface of the substrate; a step that determines the supply position from which an organic solvent is to be supplied to a peripheral portion of the resist film and dissolves the peripheral portion by the solvent supplied from the supply position to remove the same from the substrate.

Method and system configured to reduce or even nullify the degradation of images created by the projector tool turns on the optimization of the pattern-imaging by adjusting parameters and hardware of the projector to judiciously impact the placement of various image edges at different locations in the image field. Adjustments to the projector (exposure tool) include a change of a setup parameter of the exposure tool and/or scanning synchronization and/or a change of a signature of the optical system of the exposure tool determined as a result of minimizing the pre-determined cost function(s) that are parts of a comprehensive edge-placement error model.

A mirror array device, and related exposure apparatus and manufacturing method, for driving a spatial light modulator that includes: setting, in an array of mirror elements, mirror elements in a first state for turning incident light into reflected light with the same phase as that of the incident light or with a phase different by a first phase from that of the incident light and mirror elements in a second state for turning incident light into reflected light with a phase different approximately 180 from the first phase to an arrangement with a first phase distribution; and setting, in the array of mirror elements, the first mirror elements and the second mirror elements to an arrangement with a second phase distribution which is an inversion of the first phase distribution.

A magnetoresistive memory cell includes a magnetic tunnel junction pillar having a circular cross section. The pillar has a pinned magnetic layer, a tunnel barrier layer, and a free magnetic layer. A first conductive contact is disposed above the magnetic tunnel junction pillar. A second conductive contact is disposed below the magnetic tunnel junction pillar.

A photomask according to an exemplary embodiment includes: a mask substrate; and a first test pattern and a second test pattern disposed along a first edge of the mask substrate, wherein the first test pattern has a first outer shape and a first inner shape, the second test pattern has a second outer shape, and the second outer shape of the second test pattern is larger than the first inner shape of the first test pattern and smaller than the first outer shape of the first test pattern.

A method of fabricating an integrated circuit (IC) uses a first lithography technique having a first resolution and a second lithography technique having a second resolution lower than the first resolution. The method includes deriving a graph from an IC layout, the graph having vertices and edges that connect some of the vertices, the vertices representing IC patterns in the IC layout, the edges representing spacing between the IC patterns that are smaller than the second resolution. The method further includes classifying the edges into at least two types, a first type of edges representing spacing that is smaller than the first resolution, a second type of edges representing spacing that is equal to or greater than the first resolution but smaller than the second resolution.