A calibration apparatus is provided. The calibration apparatus includes a wafer carrier configured to support a substrate with a patterned layer. The patterned layer includes a first exposure area and remaining exposure areas, and each of the first and the remaining exposure areas includes a first checking mark. The calibration apparatus also includes a measurement device configured to obtain a first exposure value of the first checking mark of the first exposure area by measuring the first checking mark of the first exposure area. The calibration apparatus also includes a processing module configured to calculate first calculated values of the first checking marks of the remaining exposure areas according to the first exposure value and a standard file. The illumination device is adjusted by an adjustment device of the lithography apparatus according to the first calculated values during a lithography process.

A universal substrate for assembling ball grid array (BGA) type integrated circuit packages has a non-conducting matrix, an array of conducting vias extending between top and bottom surfaces of the matrix, and one or more instances of each of two or more different types of fiducial pairs on the top surface of the matrix. Each instance of each different fiducial pair indicates a location of a different via sub-array of the substrate for a different BGA package of a particular package size. The same substrate can be used to assemble BGA packages of different size, thereby avoiding having to design a different substrate for each different BGA package size.

A light emitting device (10) includes light emitting elements (12), conductor wirings (14), and alignment marks (18) formed on a substrate (11). The alignment marks (18) and the conductor wirings (14) are formed by printing.

An alignment system and method for aligning an object (O) having an object marker. An image of the object marker is projected onto an imaging sensor (11) having sensor elements. At least one reference marker is projected onto the imaging sensor (11). Based on image output (111) from the imaging sensor (11), respective subsets of sensor elements are determined. Based on a first subset of the sensor elements, a marker position is determined where the image of the object marker is projected onto the imaging sensor (11). Based on a second subset (Sr) of the sensor elements, a reference position is determined where the reference marker is projected onto the imaging sensor (11). The marker position correlates with a position (Xm,Ym) of the object (O) whereas the reference position does not. The object position (Xm,Ym) is determined based on the marker position relative to the reference position.

Systems, methods, and computer software are disclosed for optimizing a metrology mark. One method includes simulating an etch process based on one or more selected from: a pattern density, a microloading effect induced intra-mark variation, or a sensitivity of intra-mark variation to etch chemistry. The method can predict etch-induced process effects on the metrology mark based on the simulation of the etch process and optimize the metrology mark based on the predicted etch-induced process effects.

Aspects of the present disclosure provide an inspection system, which can include an image module and processing circuitry. The imaging module can image a wafer with a first light beam and a second light beam. The first light beam can be coaxially aligned with the second light beam, and image a first pattern located on a front side of a wafer to form a first image. The second light beam can image a second pattern located below the first pattern to form a second image via quantum tunneling imaging or infrared transmission imaging. The second light beam can have power sufficient to pass through at least a portion of a thickness of the wafer and reach the second pattern. The processing circuitry can perform image analysis on the first image and the second image to calculate an overlay value of the first and second patterns and/or defects of the wafer.

An electronic device comprising a multideck structure including a base stack of materials and one or more stacks of materials on the base stack of materials, at least one high aspect ratio feature in an array region in the base stack of materials and in the one or more stacks of materials, and overlay marks including an optical contrast material in or on only an upper portion of the base stack of materials in an overlay mark region of the electronic device is disclosed. The overlay mark region is laterally adjacent to the array region and the overlay marks are adjacent to at least one additional high aspect ratio feature in the base stack of materials. Additional electronic devices and memory devices are disclosed.

An overlay error measurement structure includes a lower-layer pattern disposed over a substrate, and an upper-layer pattern disposed over the lower-layer pattern and at least partially overlapping with the lower-layer pattern. The lower-layer pattern includes a plurality of first sub-patterns extending in a first direction and being arranged in a second direction crossing the first direction. The upper-layer pattern includes a plurality of second sub-patterns extending in the first direction and being arranged in the second direction. At least one of a pattern pitch and a pattern width of at least one of at least a part of the first sub-patterns and at least a part of the second sub-patterns varies along the second direction.