Patent classifications
G05F1/46
Controlled Power Up and Power Down of Multi-Stage Low Drop-Out Regulators
Circuits and methods that provide for fast power up and power down times in a multi-stage LDO regulator. In one embodiment, a multi-stage LDO regulator circuit includes, for each stage for which fast power up and/or power down times are desired, at least one transconductance amplifier coupled and configured to compare a primary reference voltage to one of a secondary reference voltage for the stage or an output voltage of the stage, and coupling and configuring the at least one transconductance amplifier to charge and/or discharge an associated capacitor to achieve a desired charge level within a specified time independently of the value of the associated capacitor. In general, the transconductance amplifiers of each stage are configured to charge and/or discharge an associated capacitor in synchronism with a voltage present on the primary reference voltage input.
DUAL LOOP VOLTAGE REGULATOR UTILIZING GAIN AND PHASE SHAPING
A voltage regulator that includes a first amplifier, a second amplifier, a summer, and a transistor is presented. The first amplifier has a first gain and a first frequency bandwidth, and is configured to generate a first voltage output. The second amplifier has a second gain that is lower than the first gain and a second frequency bandwidth that is higher than the first frequency bandwidth, and is configured to generate a second voltage output. The summer is configured to generate a summed voltage output. The transistor is connected to the summer and configured to generate a regulated voltage based on the summed voltage output of the summer.
Bandgap reference voltage circuit
The disclosure relates to a bandgap reference voltage circuit, in which an output reference voltage is stable with respect to temperature and other variations. Example embodiments include a bandgap reference voltage circuit comprising an output voltage circuit and a plurality, n, of offset amplifiers connected between first and second voltage rails, each of the plurality of offset amplifiers comprising a differential pair of transistors that together define an offset between an input voltage at an input and an output of the amplifier, the offset amplifiers being chained together and connected to the output voltage circuit that provides a bandgap reference voltage dependent on a sum of the offsets of the plurality of offset amplifiers.
Bandgap reference voltage circuit
The disclosure relates to a bandgap reference voltage circuit, in which an output reference voltage is stable with respect to temperature and other variations. Example embodiments include a bandgap reference voltage circuit comprising an output voltage circuit and a plurality, n, of offset amplifiers connected between first and second voltage rails, each of the plurality of offset amplifiers comprising a differential pair of transistors that together define an offset between an input voltage at an input and an output of the amplifier, the offset amplifiers being chained together and connected to the output voltage circuit that provides a bandgap reference voltage dependent on a sum of the offsets of the plurality of offset amplifiers.
Power management circuit and method for integrated circuit having multiple power domains
A power management circuit includes an inverter circuit and a latch circuit. The inverter circuit is configured to receive a first control signal from an inverter input terminal and generate a second control signal at an inverter output terminal. The first control signal carries power status information of a first supply voltage. The latch circuit has a latch supply terminal, a first latch input terminal and a second latch input terminal. The latch supply terminal is coupled to a second supply voltage becoming ready before the first supply voltage. The first latch input terminal and the second latch input terminal are coupled to the inverter output terminal and the inverter input terminal respectively. The latch circuit is configured to generate a third control signal according to respective signal levels of the first control signal and the second control signal, and accordingly perform power control of an integrated circuit.
Power management circuit and method for integrated circuit having multiple power domains
A power management circuit includes an inverter circuit and a latch circuit. The inverter circuit is configured to receive a first control signal from an inverter input terminal and generate a second control signal at an inverter output terminal. The first control signal carries power status information of a first supply voltage. The latch circuit has a latch supply terminal, a first latch input terminal and a second latch input terminal. The latch supply terminal is coupled to a second supply voltage becoming ready before the first supply voltage. The first latch input terminal and the second latch input terminal are coupled to the inverter output terminal and the inverter input terminal respectively. The latch circuit is configured to generate a third control signal according to respective signal levels of the first control signal and the second control signal, and accordingly perform power control of an integrated circuit.
Electrical power operating states for core logic in a memory physical layer
An electronic device has a memory functional block that includes memory circuits and a memory physical layer (PHY) functional block with core logic that controls operations in the memory functional block, a memory PHY voltage regulator, a system voltage regulator, and a controller. The electronic device also includes a switch having an input coupled to an output of the memory PHY voltage regulator, another input coupled to an output of the system voltage regulator, and an output coupled to a power supply input of the core logic. The controller sets the switch so that electrical power is provided from the memory PHY voltage regulator to the core logic in a full power operating state. The controller sets the switch so that electrical power is provided from the system voltage regulator to the core logic in one or more low power operating states.
Hand warmer step-less regulating circuit
The invention discloses a hand warmer step-less regulating circuit, and relates to the field of hand warmer regulating circuits; the hand warmer step-less regulating circuit comprises a comparing chip, pin 2 of the chip is connected with an NTC temperature sensor, the NTC temperature sensor is connected with a power supply VCC through resistor R16, pin 8 of the chip is connected with the power supply VCC, the power supply VCC is connected with light-emitting diode D3, and light-emitting diode D3 and the power supply VCC are connected with resistor R13 in series; pin 5 is connected with an output end of the NTC temperature sensor; by arranging the slide rheostat or an encoder, any temperature in a required area can be reached through heating, and any temperature required by a user can be maintained to realize a better temperature experience.
Hand warmer step-less regulating circuit
The invention discloses a hand warmer step-less regulating circuit, and relates to the field of hand warmer regulating circuits; the hand warmer step-less regulating circuit comprises a comparing chip, pin 2 of the chip is connected with an NTC temperature sensor, the NTC temperature sensor is connected with a power supply VCC through resistor R16, pin 8 of the chip is connected with the power supply VCC, the power supply VCC is connected with light-emitting diode D3, and light-emitting diode D3 and the power supply VCC are connected with resistor R13 in series; pin 5 is connected with an output end of the NTC temperature sensor; by arranging the slide rheostat or an encoder, any temperature in a required area can be reached through heating, and any temperature required by a user can be maintained to realize a better temperature experience.
DIFFERENTIAL AMPLIFIER CIRCUIT FOR USE IN ERROR AMPLIFIER OR COMPARATOR BEING COMPONENT OF DC TO DC CONVERTER (as amended)
A differential amplifier circuit of the present invention includes a differential input circuit including first and second transistors, and amplifies a difference voltage between a first input voltage applied to a control terminal of the first transistor and a second input voltage applied to a control terminal of the second transistor. The differential input circuit a P-channel depletion type transistor having a gate connected to the control terminal of the first transistor and a source connected to the control terminal of the second transistor, and the P-channel depletion type transistor operates as a bias current source of the differential amplifier circuit.