A pulse-width modulation control circuit includes a first transistor and a signal generator. The first transistor includes a first terminal coupled to a power source and a second terminal coupled to a first input of a controlled component. The signal generator includes a first node coupled to a gate of the first transistor. The signal generator is configured to receive a comparison value and a comparison criterion and to compare the comparison value to a counter value based on the comparison criterion. In response to the comparison value satisfying the comparison criterion with respect to the counter value, the signal generator is configured to send a control signal to the gate of the first transistor to generate a pulse edge of a pulse of a pulse-width modulated signal.

A pulse-width modulation control circuit includes a first transistor and a signal generator. The first transistor includes a first terminal coupled to a power source and a second terminal coupled to a first input of a controlled component. The signal generator includes a first node coupled to a gate of the first transistor. The signal generator is configured to receive a comparison value and a comparison criterion and to compare the comparison value to a counter value based on the comparison criterion. In response to the comparison value satisfying the comparison criterion with respect to the counter value, the signal generator is configured to send a control signal to the gate of the first transistor to generate a pulse edge of a pulse of a pulse-width modulated signal.

A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem and configured to drive an open-loop driver stage, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, and a calibration subsystem configured to calibrate at least one of a first gain of the first path and a second gain of the second path in order that the first gain and the second gain are at least approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching.

A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem and configured to drive an open-loop driver stage, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, and a calibration subsystem configured to calibrate at least one of a first gain of the first path and a second gain of the second path in order that the first gain and the second gain are at least approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching.

For calculating load resistance, a pulse generation module drives a pulse width modulation (PWM) inverter in response to a control voltage. The PWM inverter includes a U phase pole, a V phase pole, and a W phase pole. Each U, V, and W phase pole includes an upper pole device and a lower pole device. The PWM inverter turns off the U phase pole, turns on the W upper pole device, turns off the W lower pole device, and applies the control voltage to the V upper pole device and the V lower pole device. A forward drop correction module corrects the control voltage based on a feedforward compensation voltage determined from a forward voltage drop. A load resistance module calculates a load resistance for a load based on an average control voltage, an average bus voltage, and an average load feedback current.

For calculating load resistance, a pulse generation module drives a pulse width modulation (PWM) inverter in response to a control voltage. The PWM inverter includes a U phase pole, a V phase pole, and a W phase pole. Each U, V, and W phase pole includes an upper pole device and a lower pole device. The PWM inverter turns off the U phase pole, turns on the W upper pole device, turns off the W lower pole device, and applies the control voltage to the V upper pole device and the V lower pole device. A forward drop correction module corrects the control voltage based on a feedforward compensation voltage determined from a forward voltage drop. A load resistance module calculates a load resistance for a load based on an average control voltage, an average bus voltage, and an average load feedback current.

A hybrid numeric-analog clock synchronizer for establishing a clock or carrier locked to a frequency reference. The clock synchronizer is typically a clock multiplier and a jitter attenuator. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip.

A hybrid numeric-analog clock synchronizer for establishing a clock or carrier locked to a frequency reference. The clock synchronizer is typically a clock multiplier and a jitter attenuator. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip.

A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem and configured to drive an open-loop driver stage, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, and a calibration subsystem configured to calibrate at least one of a first gain of the first path and a second gain of the second path in order that the first gain and the second gain are at least approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching.

A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem and configured to drive an open-loop driver stage, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, and a calibration subsystem configured to calibrate at least one of a first gain of the first path and a second gain of the second path in order that the first gain and the second gain are at least approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching.