The present disclosure relates to a method and an apparatus for approximating non-linear function. In some embodiments, an exemplary processing unit includes: one or more registers for storing a lookup table (LUT) and one or more operation elements communicatively coupled with the one or more registers. The LUT includes a control state and a plurality of data entries. The one or more operation elements are configured to: receive an input operand; select one or more bits from the input operand; select a data entry from the plurality of data entries using the one or more bits; and determine an approximation value of a non-linear activation function for the input operand using the data entry.

A filter for video coding is configured for processing a block for generation of a filtered block, where the block comprises a plurality of pixels. The filter includes one or more processor configured to: scan a current pixel of the block and its neighboring pixels of the current pixel according to a predefined scan template, obtain spectrum components by performing transform for the current pixel and its neighboring pixels, obtain filtered spectrum components based on a filtering parameter and the spectrum components, obtain filtered pixels by performing inverse transform for the filtered spectrum components, and generate a filtered block based on the filtered pixels.

A filter for video coding is configured for processing a block for generation of a filtered block, where the block comprises a plurality of pixels. The filter includes one or more processor configured to: scan a current pixel of the block and its neighboring pixels of the current pixel according to a predefined scan template, obtain spectrum components by performing transform for the current pixel and its neighboring pixels, obtain filtered spectrum components based on a filtering parameter and the spectrum components, obtain filtered pixels by performing inverse transform for the filtered spectrum components, and generate a filtered block based on the filtered pixels.

The present disclosure may improve contrast and deep black by efficiently controlling local dimming in consideration of the ratio of a black image data and the non-uniformity in the area between blocks.

The present disclosure may improve contrast and deep black by efficiently controlling local dimming in consideration of the ratio of a black image data and the non-uniformity in the area between blocks.

An image processing method includes: detecting repetition numbers of each image frame of an input image frame sequence, wherein the input image frame sequence includes sequentially inputted at least one first image frame and at least one second image frame, and image data of each first image frame is different from image data of each second image frame; determining a first lookup table according to a first repetition numbers of the at least one first image frame, wherein the first lookup table indicates a plurality of sets of compensation calculations; and using a first set of compensation calculations in the sets of compensation calculations to process the at least one first image frame according to a second repetition numbers of the at least one second image frame.

An image processing method includes: detecting repetition numbers of each image frame of an input image frame sequence, wherein the input image frame sequence includes sequentially inputted at least one first image frame and at least one second image frame, and image data of each first image frame is different from image data of each second image frame; determining a first lookup table according to a first repetition numbers of the at least one first image frame, wherein the first lookup table indicates a plurality of sets of compensation calculations; and using a first set of compensation calculations in the sets of compensation calculations to process the at least one first image frame according to a second repetition numbers of the at least one second image frame.

Methods and/or apparatus provide for obtaining intrinsics and extrinsics of a plurality of cameras arranged to capture a scene and based thereon, generate a voxel representation of the scene; obtaining extrinsics and intrinsics of a virtual camera; mapping the extrinsics and intrinsics of the virtual camera to at least one voxel surface defined in a data structure and to identify at least one camera pair suitable for obtaining depth data for that voxel surface based on the corresponding camera pair identifier; and receiving an input from the mapping unit, and in response obtaining images captured by the cameras in the at least one camera pair identified as being suitable for reconstructing the scene from the viewpoint of the virtual camera, and to generate an image of the scene from the viewpoint of the virtual camera based on the obtained images.

Embodiments of a telemetry device and methods to convert a binary floating point number to a compressed number is described herein. The binary floating point number may comprise a mantissa and an exponent. The telemetry device may determine a first number based on a product of the exponent and a constant, wherein the constant may be proportional to a logarithm of the number two. The telemetry device may determine a second number using one or more bits of the mantissa as an index into a predetermined lookup table. Values of the lookup table may be proportional to logarithms of candidate mantissa values. The telemetry device may determine the compressed number based on rounding of a sum. The sum may include the first and second numbers. The rounding may be based on a predetermined step size.

The present disclosure relates to a carry chain logic system that leverages carry in and carry out signals from logic blocks to implement logic functions on programmable hardware (e.g., FPGA hardware). In particular, implementations of the carry chain logic system facilitate implementation of logic gates (e.g., AND/OR gates) having high number of input signals without incurring routing delays caused by routing output signals between logic components implemented across different logic stages. For example, implementations described herein involve feeding carry out signals between adders of a logic chain across multiple logic components on a common logic stage, thus reducing routing penalties caused by routing signals via a routing fabric of the programmable hardware.