The present disclosure concerns a method of executing a SoftMax function, the method comprising: (i) pre-storing in memory M fraction components (fc.sub.j) in binary form, derived from the expression 2.sup.(j/M), said fc.sub.j forming a lookup table (T) of size M; (ii) calculating, for each z.sub.i, an element y.sub.i of a number of the form 2.sup.y.sup.i; (iii) separating y.sub.i into an integral part (int.sub.i) and a fractional part (fract.sub.i); (iv) determining a lookup index (ind.sub.i) that corresponds to fract.sub.i scaled by the size M; (v) retrieving a fraction component fc.sub.i from T with ind.sub.i; (vi) generating, in a result register, a binary number representative of the exponential value of said z.sub.i, by combining said fc.sub.i retrieved from T and said int.sub.i; (v) adding the K result registers corresponding to z.sub.i into a sum register R7; and (vi) determining the K probability values p.sub.i from the K result registers and the sum register.

Numerous examples of a precision programming apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. In one example, a neuron output circuit for providing a current to program as a weight value in a selected memory cell in a vector-by-matrix multiplication array is disclosed, the neuron output circuit comprising a first adjustable current source to generate a scaled current in response to a neuron current to implement a positive weight, and a second adjustable current source to generate a scaled current in response to a neuron current to implement a negative weight.

Numerous examples of a precision programming apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. In one example, a neuron output circuit for providing a current to program as a weight value in a selected memory cell in a vector-by-matrix multiplication array is disclosed, the neuron output circuit comprising a first adjustable current source to generate a scaled current in response to a neuron current to implement a positive weight, and a second adjustable current source to generate a scaled current in response to a neuron current to implement a negative weight.

A filter for video coding is provided, where the filter is configured for processing a block for generation of a filtered block, and the block comprises a plurality of pixels. The filter includes one or more processor configured to: scan, according to a predefined scan template, to obtain a current pixel of the block and its neighboring pixels of the current pixel; obtain spectrum components by performing transform for the current pixel and its neighboring pixels; obtain filtered spectrum components based on a filtering parameter and the spectrum components; obtain filtered pixels by performing inverse transform for the filtered spectrum components; and generate a filtered block based on the filtered pixels. The filter is provided allowing improving the efficiency for video coding.

A filter for video coding is provided, where the filter is configured for processing a block for generation of a filtered block, and the block comprises a plurality of pixels. The filter includes one or more processor configured to: scan, according to a predefined scan template, to obtain a current pixel of the block and its neighboring pixels of the current pixel; obtain spectrum components by performing transform for the current pixel and its neighboring pixels; obtain filtered spectrum components based on a filtering parameter and the spectrum components; obtain filtered pixels by performing inverse transform for the filtered spectrum components; and generate a filtered block based on the filtered pixels. The filter is provided allowing improving the efficiency for video coding.

The present disclosure may improve contrast and deep black by efficiently controlling local dimming in consideration of the ratio of a black image data and the non-uniformity in the area between blocks.

The present disclosure may improve contrast and deep black by efficiently controlling local dimming in consideration of the ratio of a black image data and the non-uniformity in the area between blocks.

Systems and methods related to charge locking circuits and a control system for qubits are provided. A system for controlling qubit gates includes a first packaged device comprising a quantum device including a plurality of qubit gates, where the quantum device is configured to operate at a cryogenic temperature. The system further includes a second packaged device comprising a control circuit configured to operate at the cryogenic temperature, where the first packaged device is coupled to the second packaged device, and where the control circuit comprises a plurality of charge locking circuits, where each of the plurality of charge locking circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect such that each of the plurality of charge locking circuits is configured to provide a voltage signal to at least one qubit gate.

The disclosed embodiments relate to a system that compactly stores time-series sensor signals. During operation, the system receives original time-series signals comprising sequences of observations obtained from sensors in a monitored system. Next, the system formulizes the original time-series sensor signals to produce a set of equations, which can be used to generate synthetic time-series signals having the same correlation structure and the same stochastic properties as the original time-series signals. Finally, the system stores the formulized time-series sensor signals in place of the original time-series sensor signals.

A processing unit to support inference acceleration for machine learning (ML) comprises an inline post processing unit configured to accept and maintain one or more lookup tables for performing each of one or more non-linear mathematical operations. The inline post processing unit is further configured to accept data from a set of registers maintaining output from a processing block instead of streaming the data from an on-chip memory (OCM), perform the one or more non-linear mathematical operations on elements of the data from the processing block via their corresponding lookup tables, and stream post processing result of the one or more non-linear mathematical operations back to the OCM after the one or more non-linear mathematical operations are complete.