Embodiments include an apparatus comprising an execution unit coupled to a memory, a microcode controller, and a hardware controller. The microcode controller is to identify a global power and performance hint in an instruction stream that includes first and second instruction phases to be executed in parallel, identify a local hint based on synchronization dependence in the first instruction phase, and use the first local hint to balance power consumption between the execution unit and the memory during parallel executions of the first and second instruction phases. The hardware controller is to use the global hint to determine an appropriate voltage level of a compute voltage and a frequency of a compute clock signal for the execution unit during the parallel executions of the first and second instruction phases. The first local hint includes a processing rate for the first instruction phase or an indication of the processing rate.

Embodiments include an apparatus comprising an execution unit coupled to a memory, a microcode controller, and a hardware controller. The microcode controller is to identify a global power and performance hint in an instruction stream that includes first and second instruction phases to be executed in parallel, identify a local hint based on synchronization dependence in the first instruction phase, and use the first local hint to balance power consumption between the execution unit and the memory during parallel executions of the first and second instruction phases. The hardware controller is to use the global hint to determine an appropriate voltage level of a compute voltage and a frequency of a compute clock signal for the execution unit during the parallel executions of the first and second instruction phases. The first local hint includes a processing rate for the first instruction phase or an indication of the processing rate.

An electronic control unit (ECU) includes a processor, a Controller Area Network (CAN) controller, clock gating logic, and security gating logic. The CAN controller having a status and configured to receive data and control signals from the processor, and a clock signal, package the data to create a CAN protocol frame held in at least one transmit buffer, and shift the CAN protocol frame to a CAN transceiver that is configured to transmit the CAN protocol frame to a CAN bus. The security gating logic configured to, in response to the status of the CAN controller being active, inhibit disabling the clock signal.

An electronic control unit (ECU) includes a processor, a Controller Area Network (CAN) controller, clock gating logic, and security gating logic. The CAN controller having a status and configured to receive data and control signals from the processor, and a clock signal, package the data to create a CAN protocol frame held in at least one transmit buffer, and shift the CAN protocol frame to a CAN transceiver that is configured to transmit the CAN protocol frame to a CAN bus. The security gating logic configured to, in response to the status of the CAN controller being active, inhibit disabling the clock signal.

The invention introduces a non-transitory computer-readable storage medium for adjusting operating frequencies when executed by a processing unit of a device, containing program code to: collect an interface-activity parameter comprising information about data transmissions on a host access interface and/or a flash access interface; select one from multiple frequencies according to the interface-activity parameter; and drive a clock generator to output a clock signal at the selected frequency, thereby enabling the host access interface and/or the flash access interface to operate at an operating frequency.

The invention introduces a non-transitory computer-readable storage medium for adjusting operating frequencies when executed by a processing unit of a device, containing program code to: collect an interface-activity parameter comprising information about data transmissions on a host access interface and/or a flash access interface; select one from multiple frequencies according to the interface-activity parameter; and drive a clock generator to output a clock signal at the selected frequency, thereby enabling the host access interface and/or the flash access interface to operate at an operating frequency.

A circuit for controlling a switch of a power converter includes a first clock signal generator configured to generate a first clock signal and a switching signal generator configured to generate a switching signal to control the switch of the power converter based on the first clock signal. The circuit further includes error detection circuitry configured to output an error indication and a second clock signal generator configured to generate, in response to the error indication, a second clock signal that comprises an edge of a clock cycle of the second clock signal that corresponds to when the switching signal deactivates the switch of the power converter plus a time delay. The switching signal generator is configured to generate the switching signal to control the switch of the power converter further based on the second clock signal in response to the error indication being output by the error detection circuitry.

A circuit for controlling a switch of a power converter includes a first clock signal generator configured to generate a first clock signal and a switching signal generator configured to generate a switching signal to control the switch of the power converter based on the first clock signal. The circuit further includes error detection circuitry configured to output an error indication and a second clock signal generator configured to generate, in response to the error indication, a second clock signal that comprises an edge of a clock cycle of the second clock signal that corresponds to when the switching signal deactivates the switch of the power converter plus a time delay. The switching signal generator is configured to generate the switching signal to control the switch of the power converter further based on the second clock signal in response to the error indication being output by the error detection circuitry.

A clock calibration method and apparatus is provided, where the method includes a terminal device uses first timing information, adjusts second timing information of the terminal device based on reference timing information, and when determining that a first condition is met, switches from using the first timing information to using the second timing information. The first timing information is primary timing information, the second timing information is standby timing information, and the first condition includes that: the first timing information is different from the reference timing information, and the second timing information is the same as the reference timing information; or the first timing information is different from the second timing information; or the first timing information is different from the reference timing information.

A clock calibration method and apparatus is provided, where the method includes a terminal device uses first timing information, adjusts second timing information of the terminal device based on reference timing information, and when determining that a first condition is met, switches from using the first timing information to using the second timing information. The first timing information is primary timing information, the second timing information is standby timing information, and the first condition includes that: the first timing information is different from the reference timing information, and the second timing information is the same as the reference timing information; or the first timing information is different from the second timing information; or the first timing information is different from the reference timing information.