A system for data transmission includes a physical (PHY) layer which has a rate detection module which determines an adopted clock rate. The rate detection module provides a rate detection signal indicative of the adopted clock rate. The PHY layer includes a reference clock generator which has an input coupled to receive the rate detection signal and an output to provide a reference clock output. The PHY layer includes a PHY interface which has a first input coupled to receive the reference clock output, a data input and a data output. The PHY interface receives data from a MAC interface at the data input and transmits data to the MAC interface through the data output responsive to the reference clock output.

A system for data transmission includes a physical (PHY) layer which has a rate detection module which determines an adopted clock rate. The rate detection module provides a rate detection signal indicative of the adopted clock rate. The PHY layer includes a reference clock generator which has an input coupled to receive the rate detection signal and an output to provide a reference clock output. The PHY layer includes a PHY interface which has a first input coupled to receive the reference clock output, a data input and a data output. The PHY interface receives data from a MAC interface at the data input and transmits data to the MAC interface through the data output responsive to the reference clock output.

A clock circuit constructed in a processor integrated circuit includes a phase lock loop PLL, a clock tree, and a clock grid. The clock tree includes a plurality of clock buffers in a layered structure, The clock tree is configured to receive a first clock signal clk_1 that is output by the phase lock loop PLL, and to output a second clock signal clk_2. A plurality of child node circuits (400) are disposed on some nodes of the clock grid, and are configured to generate a third clock signal clk_3 based on the second clock signal clk_2. The clock grid (330) and the clock tree (320) are distributed on multiple dies in a three-dimensional structure of the processor integrated circuit.

The present disclosure relates to a dual-clock generation circuit and method and an electronic device, and relates to the technical field of integrated circuits. The dual-clock generation circuit includes: a first inverter module, configured to access a first signal and output a first clock output signal; a second inverter module, configured to access a second signal and output a second clock output signal, where the first signal and the second signal are opposite clock signals; a first feedforward buffer, disposed between an input terminal of the first inverter module and an output terminal of the second inverter module, and configured to transmit the first signal to compensate for the second clock output signal.

The present disclosure relates to a dual-clock generation circuit and method and an electronic device, and relates to the technical field of integrated circuits. The dual-clock generation circuit includes: a first inverter module, configured to access a first signal and output a first clock output signal; a second inverter module, configured to access a second signal and output a second clock output signal, where the first signal and the second signal are opposite clock signals; a first feedforward buffer, disposed between an input terminal of the first inverter module and an output terminal of the second inverter module, and configured to transmit the first signal to compensate for the second clock output signal.

The present invention provides a DP-out adapter including a decoder, a clock signal generating circuit, a DP signal generating circuit and a symbol counter value comparator. The decoder is configured to decode a USB signal to generate a plurality of packets. The clock signal generating circuit is configured to generate a clock signal. The DP signal generating circuit is configured to generate a DP signal according to the packets, and output the DP signal according to the clock signal. The symbol counter value comparator is configured to generate a first counter value according to a number of symbols corresponding to the plurality of packets, and use the clock signal to count to obtain a second counter value, and compare the first counter value and the second counter value to generate a control signal to the clock signal generating circuit to adjust a frequency of the clock signal.

The present disclosure describes techniques for incorporating pipelined DSP blocks or other types of embedded functions into a logic circuit with a slower clock rate without any clock crossing complexities, and at the same time managing the power consumption of the more complex design that results from it. The techniques include generating a faster clock or several faster clocks that may have a faster clock rate than the clock used by the logic circuit and that may be used as clock input to the embedded pipelined DSP blocks. In addition, the present disclosure describes techniques for generating, improving, and using the faster clock to sample the output of a logic circuit using pulses of generated faster clock, which may allow to increase the clock frequency of the circuit to an optimal level, while maintaining functional correctness.

The present disclosure describes techniques for incorporating pipelined DSP blocks or other types of embedded functions into a logic circuit with a slower clock rate without any clock crossing complexities, and at the same time managing the power consumption of the more complex design that results from it. The techniques include generating a faster clock or several faster clocks that may have a faster clock rate than the clock used by the logic circuit and that may be used as clock input to the embedded pipelined DSP blocks. In addition, the present disclosure describes techniques for generating, improving, and using the faster clock to sample the output of a logic circuit using pulses of generated faster clock, which may allow to increase the clock frequency of the circuit to an optimal level, while maintaining functional correctness.

A delay adjustment cell is disposed in a channel of at least one regional clock of a chip clock architecture, and the delay adjustment cell includes a plurality of parallel delay paths with different delay values. The delay adjustment cell gates one of the delay paths based on an obtained configuration signal such that a connected regional clock has a corresponding target delay, and a target delay of each regional clock corresponds to a clock skew mode of the programmable logic chip. A clock skew between different regional clocks is adjusted by controlling the gated delay path in the delay adjustment cell, such that a clock skew of the chip can be adjusted in a relatively large range. Under the same resource configuration, different path choices of the delay adjustment cell lead to different clock skews to meet different clock skew modes in different application scenarios.

A delay adjustment cell is disposed in a channel of at least one regional clock of a chip clock architecture, and the delay adjustment cell includes a plurality of parallel delay paths with different delay values. The delay adjustment cell gates one of the delay paths based on an obtained configuration signal such that a connected regional clock has a corresponding target delay, and a target delay of each regional clock corresponds to a clock skew mode of the programmable logic chip. A clock skew between different regional clocks is adjusted by controlling the gated delay path in the delay adjustment cell, such that a clock skew of the chip can be adjusted in a relatively large range. Under the same resource configuration, different path choices of the delay adjustment cell lead to different clock skews to meet different clock skew modes in different application scenarios.