A control system for factory automation includes a first unit and a second unit that exchange data with each other, and a synchronization module that synchronizes a control counter included in the first unit and a control counter included in the second unit using a clock. Each of the units includes an information storage that stores information on conversion for calculating a time from a counter value of the counter of the unit, the information being shared between the units.

Methods for improving timing in memory devices are disclosed. A method may include sampling a command signal according to a clock signal to obtain standard-timing commands. The method may also include sampling the command signal according to an adjusted clock signal to obtain time-adjusted commands. The method may also include comparing the standard-timing commands and the time-adjusted commands. The method may also include determining an improved timing for the clock signal based on the comparison of the standard-timing commands and the time-adjusted commands. The method may also include adjusting the clock signal based on the improved timing. Associated systems and methods are also disclosed.

Methods for improving timing in memory devices are disclosed. A method may include sampling a command signal according to a clock signal to obtain standard-timing commands. The method may also include sampling the command signal according to an adjusted clock signal to obtain time-adjusted commands. The method may also include comparing the standard-timing commands and the time-adjusted commands. The method may also include determining an improved timing for the clock signal based on the comparison of the standard-timing commands and the time-adjusted commands. The method may also include adjusting the clock signal based on the improved timing. Associated systems and methods are also disclosed.

Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.

Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.

The present disclosure discloses an on-chip synchronous self-repairing system based on a low-frequency reference signal. The system adopts a dual-input PLL stellate coupled structure or a dual-input PLL butterfly-shaped coupled structure, and delay of the whole loop is made to be an integral multiple of the reference signal by synchronizing the transmitted reference signal with the received reference signal, so as to ensure synchronization of local oscillation signal of each IC chip. The transmission wire based on an adjustable left-handed material is used as a delay wire to connect the dual-input PLL, thereby achieving low loss and reducing the physical distance of the delay wire. The system has the advantages of small area, low loss, strong adaptability and strict synchronization in various environments.

A digital value obtained from a preceding circuit element is temporarily stored and made available for a subsequent circuit element at a controlled moment of time. The digital value is received through a data input. A triggering signal is also received, a triggering edge of which defines an allowable time limit before which a digital value must be available at said data input to become available for said subsequent circuit element. Between first and second pulse-enabled subregister stages, an internal digital value from the first pulse-enabled subregister stage and information of the changing moment of said digital value at the data input in relation to said allowable time limit are used to ensure passing a valid internal digital value to the second pulse-enabled subregister stage. Said second pulse-enabled subregister stage makes said valid internal digital value available for said subsequent circuit element. A timing event observation signal is output as an indicator of said digital value at said data input having changed within a time window that begins at said allowable time limit and is shorter than one cycle of said triggering signal.

While a host vehicle is within an area, a target vehicle is identified based on detecting the target vehicle within the area. Upon determining a component output, first instructions specifying the component output and a target vehicle component are provided to the target vehicle. A host clock for the host vehicle is synchronized with a clock maintained by a remote server computer. Then second instructions specifying to initiate, at a target time, actuation of the target vehicle component to provide the component output are provided to the target vehicle. Then a host vehicle component is actuated at a host time to provide the component output.

While a host vehicle is within an area, a target vehicle is identified based on detecting the target vehicle within the area. Upon determining a component output, first instructions specifying the component output and a target vehicle component are provided to the target vehicle. A host clock for the host vehicle is synchronized with a clock maintained by a remote server computer. Then second instructions specifying to initiate, at a target time, actuation of the target vehicle component to provide the component output are provided to the target vehicle. Then a host vehicle component is actuated at a host time to provide the component output.

A low power sensing device includes a sensor including key sensors configured to generate sensing signals, respectively, a reference sensor configured to generate a reference sensing signal, a two-state clock generator configured to generate a first clock signal and a second clock signal having clock frequencies different from each other, and a controller. The controller is configured to receive the sensing signals and the reference sensing signal, control enable operations and disable operations of the sensor and the reference sensor based on a first operation mode and a second operation mode each repeatedly performed for a predetermined time, receive the first clock signal during the first operation mode, and receive the second clock signal during the second operation mode.