An electrical circuit, having: an oscillating element configured to provide a clock signal; and a clock synchronization unit configured to adapt the clock signal based on a reference signal; wherein the clock synchronization unit is configured to extract from an alternating signal the reference signal.

A method monitors a sensor clock signal in a sensor unit, which is generated and output for a data transfer between the sensor unit and a control unit with a predefined period duration. A reference clock signal having a predefined reference period duration is received. The sensor clock signal is compared to the reference clock signal. Based on the comparison, a deviation of the current period duration of the sensor clock signal from a target period duration is detected. Based on the detected deviation, a counting pulse or a reset pulse is emitted.

A method monitors a sensor clock signal in a sensor unit, which is generated and output for a data transfer between the sensor unit and a control unit with a predefined period duration. A reference clock signal having a predefined reference period duration is received. The sensor clock signal is compared to the reference clock signal. Based on the comparison, a deviation of the current period duration of the sensor clock signal from a target period duration is detected. Based on the detected deviation, a counting pulse or a reset pulse is emitted.

This application discloses a clock synchronization method and a related apparatus in a distributed system. The distributed system includes a plurality of nodes, and the plurality of nodes include a master node and a plurality of slave nodes. The master node obtains a plurality of local clock offsets, where each of the plurality of local clock offsets indicates a clock offset between two nodes in the distributed system. The master node determines a global clock offset of a target slave node relative to the master node based on the plurality of local clock offsets, and sends the global clock offset to the target slave node. The target slave node obtains a clock reference value of a local clock, and then performs clock synchronization based on the clock reference value and the global clock offset.

This application discloses a clock synchronization method and a related apparatus in a distributed system. The distributed system includes a plurality of nodes, and the plurality of nodes include a master node and a plurality of slave nodes. The master node obtains a plurality of local clock offsets, where each of the plurality of local clock offsets indicates a clock offset between two nodes in the distributed system. The master node determines a global clock offset of a target slave node relative to the master node based on the plurality of local clock offsets, and sends the global clock offset to the target slave node. The target slave node obtains a clock reference value of a local clock, and then performs clock synchronization based on the clock reference value and the global clock offset.

Methods and systems for performing current sense compensation for one or more power stages in a multiphase voltage regulator are described. A controller can be connected to a plurality of power stages through a communication interface. The controller can generate a data packet including a command to obtain temperature information and an address that identifies a specific power stage among the plurality of power stages. The controller can send the data packet to the plurality of power stages using the communication interface. The controller can receive temperature information of the specific power stage from the specific power stage through the communication interface. The controller can compensate a sensed current of the specific power stage based on the received temperature information of the specific power stage.

Methods and systems for performing current sense compensation for one or more power stages in a multiphase voltage regulator are described. A controller can be connected to a plurality of power stages through a communication interface. The controller can generate a data packet including a command to obtain temperature information and an address that identifies a specific power stage among the plurality of power stages. The controller can send the data packet to the plurality of power stages using the communication interface. The controller can receive temperature information of the specific power stage from the specific power stage through the communication interface. The controller can compensate a sensed current of the specific power stage based on the received temperature information of the specific power stage.

An example device comprising: first clock divider circuitry to be coupled to a first clock; first counter circuitry configured to be coupled to the first clock divider circuitry, the first counter circuitry configured to increment based on the first clock and a second clock; second clock divider circuitry to be coupled to a third clock; second counter circuitry configured to be coupled to the second clock divider circuitry, the second counter circuitry configured to increment based on the third clock and the second clock; and comparison circuitry coupled to the first and second counter circuitry.

An example device comprising: first clock divider circuitry to be coupled to a first clock; first counter circuitry configured to be coupled to the first clock divider circuitry, the first counter circuitry configured to increment based on the first clock and a second clock; second clock divider circuitry to be coupled to a third clock; second counter circuitry configured to be coupled to the second clock divider circuitry, the second counter circuitry configured to increment based on the third clock and the second clock; and comparison circuitry coupled to the first and second counter circuitry.

A circuit and method are provided for setting a phase relationship between a first signal and a second signal having a known frequency relationship to a master signal but having an unknown phase relationship to each other. One or more phase signals is generated based on the master signal, the phase signals having different phases from each other. One of these phase signals is selected based on the phase of the first signal and a target phase delay between the first signal and second signal. The second signal is generated based on the phase and frequency of the selected phase signal.