G06F1/14

Parallel processing device
11526432 · 2022-12-13 · ·

There is provided a parallel processing device which allows consecutive parallel data processing to be performed. The parallel processing device includes: a plurality of addition units configured to selectively receive input data among output data from the plurality of input units according to configuration values for each addition unit of the plurality of addition units, and perform addition operation for the input data in parallel; and the plurality of the delay units configured to delay input data for one cycle. Each delay unit of the plurality of the delay units delays output data from each addition unit of the plurality of addition units and outputs the delayed output data to each input unit of the plurality of input units.

Parallel processing device
11526432 · 2022-12-13 · ·

There is provided a parallel processing device which allows consecutive parallel data processing to be performed. The parallel processing device includes: a plurality of addition units configured to selectively receive input data among output data from the plurality of input units according to configuration values for each addition unit of the plurality of addition units, and perform addition operation for the input data in parallel; and the plurality of the delay units configured to delay input data for one cycle. Each delay unit of the plurality of the delay units delays output data from each addition unit of the plurality of addition units and outputs the delayed output data to each input unit of the plurality of input units.

TIME ALIGNMENT IN DIRECTOR-BASED DATABASE SYSTEM FOR TRANSACTIONAL CONSISTENCY
20220391377 · 2022-12-08 ·

Techniques are disclosed relating to a database system includes worker nodes operable to perform transactions and director nodes operable to ensure transactional consistency for the transactions. A worker node may receive a request to perform a transaction involving writing a record. The worker node may then issue, to director nodes of the database system, a request for information that facilitates performance of an operation for the transaction. A director node may determine whether to approve the request based on whether the operation could cause transactional inconsistency in the database system. The worker node may proceed to perform the operation for the transaction in response to receiving approval responses from a majority of the director nodes, with none of the received responses indicating a disapproval of the transaction.

TIME PROPOSALS IN DIRECTOR-BASED DATABASE SYSTEM FOR TRANSACTIONAL CONSISTENCY
20220391378 · 2022-12-08 ·

Techniques are disclosed relating to a database system includes worker nodes operable to perform transactions and director nodes operable to ensure transactional consistency for the transactions. A worker node may receive a request to perform a transaction involving writing a record. The worker node may then issue, to director nodes of the database system, a request for information that facilitates performance of an operation for the transaction. A director node may determine whether to approve the request based on whether the operation could cause transactional inconsistency in the database system. The worker node may proceed to perform the operation for the transaction in response to receiving approval responses from a majority of the director nodes, with none of the received responses indicating a disapproval of the transaction.

Time synchronization using skew estimation
11520372 · 2022-12-06 · ·

Techniques are disclosed for performing time synchronization for a plurality of computing devices without relying upon a minimum measured delay. In one example, processing circuitry obtains time stamp data in accordance with an iteration of a synchronization operation for a timing protocol, wherein the time stamp data describes one or more measured delays for a path between a first computing device and a second computing device, computes a skewness estimate from the time stamp data using a regression analysis, the skewness estimate comprising a frequency difference between a first clock at the first computing device and a second clock at the second computing device, computes an offset estimate between the first clock and the second clock by applying a prediction model to the skewness estimate; and corrects at least one of the first clock or the second clock based at least on the offset estimate.

Time synchronization using trust aggregation
11595405 · 2023-02-28 · ·

A method for synchronizing time may include receiving initial time information including an initial timestamp from a first device, adjusting a clock of the device with the initial time information, storing the initial time information as an earliest possible time, receiving additional time information, including a second timestamp, from a second device, and evaluating the additional time information. When the evaluated additional time information includes information that is unacceptable, the method may further include adjusting the clock with the second timestamp, and replacing the earliest possible time with the second timestamp. When the evaluated additional time information includes information that is acceptable, the method may further include adjusting the clock with the additional time information, and replacing the earliest possible time with the additional time information. The initial time information and additional time information may be respectively determined based on reconciled time data received from two or more proximate devices.

Method and system for correcting clock skew using precision time protocol
11509411 · 2022-11-22 · ·

The disclosure relates to method and system for correcting a clock skew in a slave device using a precision time protocol (PTP). The method includes determining an uplink delay and a downlink delay, based on at least two packet transactions in the PTP protocol and conducted between the slave device and a master device within a pre-defined accumulator time window. The method further includes determining a change in the uplink/downlink delay with respect to a reference uplink/downlink delay. The reference uplink/downlink delay correspond to a first pre-defined accumulator time window at a start of the slave device, or to a last pre-defined accumulator time window during a previous correction of the clock skew. The method further includes correcting the clock skew upon determining the change in the uplink delay to be about same in magnitude as and to be in opposite direction to the change in the downlink delay.

Method and system for correcting clock skew using precision time protocol
11509411 · 2022-11-22 · ·

The disclosure relates to method and system for correcting a clock skew in a slave device using a precision time protocol (PTP). The method includes determining an uplink delay and a downlink delay, based on at least two packet transactions in the PTP protocol and conducted between the slave device and a master device within a pre-defined accumulator time window. The method further includes determining a change in the uplink/downlink delay with respect to a reference uplink/downlink delay. The reference uplink/downlink delay correspond to a first pre-defined accumulator time window at a start of the slave device, or to a last pre-defined accumulator time window during a previous correction of the clock skew. The method further includes correcting the clock skew upon determining the change in the uplink delay to be about same in magnitude as and to be in opposite direction to the change in the downlink delay.

Random number generator, random number generating circuit, and random number generating method

A random number generator, a random number generating circuit, and a random number generating method are provided. The random number generating circuit includes the random number generator and executes the random number generating method. The random number generator includes a shift register having N storage elements and a combinational logic circuit. The N storage elements receive a random seed in a static state and repetitively perform a bit shift operation in a plurality of clock cycles. The combinational logic circuit generates an output sequence based on the random seed and a random bitstream received from an external source.

Random number generator, random number generating circuit, and random number generating method

A random number generator, a random number generating circuit, and a random number generating method are provided. The random number generating circuit includes the random number generator and executes the random number generating method. The random number generator includes a shift register having N storage elements and a combinational logic circuit. The N storage elements receive a random seed in a static state and repetitively perform a bit shift operation in a plurality of clock cycles. The combinational logic circuit generates an output sequence based on the random seed and a random bitstream received from an external source.