A semiconductor device includes a switching element, a control circuit, and a first and second temperature detectors. The control circuit controls the switching element and have an overcurrent detection circuit for the switching element. The first temperature detector detects the temperature of the switching element and the second temperature detector detects the temperature of the control circuit. The control circuit includes a reference correction circuit for correcting an overcurrent reference value of the overcurrent detection circuit on the basis of a first detection value and a second detection value detected by the first and second temperature detectors and outputting a corrected overcurrent reference value.

An information handling system includes resistive short detection circuitry that measures a first amount of power provided by a power supply system, and measures a second amount of power drawn by components. The resistive short detection circuitry compares the first amount of power with the second amount of power. In response to first amount of power being greater than the second amount of power, the resistive short detection circuitry determines that a short exists within the information handling system.

The present disclosure describes systems and methods for detecting malware. More particularly, the system includes a monitoring device that monitors side-channel activity of a target device. The monitoring device that can work in conjunction with (or independently of) a cloud-based security analytics engine to perform anomaly detection and classification on the side-channel activity. For example, the monitoring device can calculate a first set of features that are then transmitted to the security analytics engine for anomaly detection and classification.

The present disclosure describes systems and methods for detecting malware. More particularly, the system includes a monitoring device that monitors side-channel activity of a target device. The monitoring device that can work in conjunction with (or independently of) a cloud-based security analytics engine to perform anomaly detection and classification on the side-channel activity. For example, the monitoring device can calculate a first set of features that are then transmitted to the security analytics engine for anomaly detection and classification.

A computer system including a PCH (platform controller hub), a CPLD (complex programmable logic device), a first switch and a processor, and a control method are provided to control the operation frequency of the processor. The CPLD is coupled to the PCH and the first switch. The processor is coupled to the first switch. The PCH produces and outputs a second control signal according to the first firmware and a first control signal from a command input unit. The CPLD produces and outputs a third control signal according to the second firmware and the second control signal. The first switch receives the third control signal and is turned on to output a triggering signal when the third control signal is valid. The processor includes a PROCHOT pin. The processor receives the triggering signal and triggers the PROCHOT pin for frequency control.

A computer system including a PCH (platform controller hub), a CPLD (complex programmable logic device), a first switch and a processor, and a control method are provided to control the operation frequency of the processor. The CPLD is coupled to the PCH and the first switch. The processor is coupled to the first switch. The PCH produces and outputs a second control signal according to the first firmware and a first control signal from a command input unit. The CPLD produces and outputs a third control signal according to the second firmware and the second control signal. The first switch receives the third control signal and is turned on to output a triggering signal when the third control signal is valid. The processor includes a PROCHOT pin. The processor receives the triggering signal and triggers the PROCHOT pin for frequency control.

Systems and methods are disclosed for determining an input voltage level of an input voltage received by a connection cable. A monitoring component may determine whether the input voltage level matches one of a plurality of voltage levels. The connection cable may include an indicator component that may indicate which of the plurality of voltage levels matches the input voltage level.

A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.

A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.

An embodiment of the present disclosure relates to a power supply interface comprising: a converter delivering a first DC voltage; a resistor connected between the converter and an output terminal of the interface delivering a second DC voltage; a first circuit delivering a second signal representative of a difference between the second DC voltage and a voltage threshold when a first signal is in a first state, and at a default value otherwise; a second circuit delivering a third signal representative of a value of a current in first resistor multiplied by a gain of the third circuit, and modifying the gain based on the second signal; and a third circuit configured to deliver a signal for controlling the converter based at least on the third signal.