The present disclosure generally relates to split, non-operational power states for a data storage device. The data storage device can transition between the split, non-operational power states without advertising the transition to the host device. The power state parameters that are advertised to the host device are adjusted such that the host device is guided to the correct power decision based on the advertised power and duration. By splitting the non-operational power states, the data storage device does not incur additional transitional energy costs for short idle durations.

In accordance with embodiments disclosed herein, there is provided systems and methods for a serial mid-speed interface. A first component includes a phase-locked loop (PLL) to receive an input clock signal and to output an output signal, an interface controller including a clock-management state machine, and a transmitter. The interface controller is to receive the input clock signal, receive the output signal from the PLL, and generate a speed-switch packet. The transmitter is to transmit a first plurality of packets to a second component at a clock rate based on the clock signal via a mid-speed interface, transmit the speed-switch packet to the second component, and transmit a second plurality of packets to the second component at a PLL rate based on the output signal, where the PLL rate is greater than the clock rate.

Processor-based systems employing local dynamic power management based on controlling performance and operating power consumption, and related methods. The processor-based system is configured to locally manage its power consumption by dynamically adjusting operating frequency and/or operating voltage of power supplied to the processor-based system. The processor-based system includes a power control circuit that is aware of the overall power budget for the processor-based system. The control processor in the processor-based system can dynamically increase the voltage level of the power supplied to the processor-based system and/or the operating frequency if the consumed power is lower than the power budget. The power control circuit can also dynamically decrease the operating frequency and/or the voltage level of the power supplied to the processor-based system if the consumed power is higher than the power budget.

A method of an electronic device are provided in which current consumption for one or more components of the electronic device is compared with a predetermined current. A first surface temperature of the electronic device is determined based on the comparison and power consumption of the one or more components. A location is detected where heat corresponding to the first surface temperature is generated. A second surface temperature of the electronic device is obtained based on power consumption of a component disposed in the electronic device corresponding to the location where the heat is generated. A target temperature is set based on the obtained second surface temperature. The component is controlled to reduce the power consumption of the component based on the target temperature.

An operational circuit of a virtual currency data processing device includes: at least two operational chip groups (31) configured to operate within respective operating voltage threshold ranges of the operational chip groups (31) to receive a communication signal which includes an issued task, perform calculations according to the issued task, and transmit a communication signal which includes a calculation result; a control module (32) configured to operate within an operating voltage threshold range of the control module (32) to transmit the communication signal which includes the issued task and receive the communication signal which includes the calculation result; at least two signal forwarding and electrical isolation modules, each of which is communicatively connected to the control module and a respective operational chip group and is configured to forward communication signals between the control module and the respective operational chip group, and isolate an operating voltage threshold of the operational chip groups from an operating voltage threshold of the control module to make the operational chip groups and the control module capable of identifying communication signals sent by each other.

A computing device includes an array of processing elements mutually connected to perform single instruction multiple data (SIMD) operations, memory cells connected to each processing element to store data related to the SIMD operations, and a cache connected to each processing element to cache data related to the SIMD operations. Caches of adjacent processing elements are connected. The same or another computing device includes rows of mutually connected processing elements to share data. The computing device further includes a row arithmetic logic unit (ALU) at each row of processing elements. The row ALU of a respective row is configured to perform an operation with processing elements of the respective row.

Power supply efficiency may be provided. First, a total power supply capacity may be determined comprising a sum of a plurality of supply capacities respectively corresponding to a plurality of power supplies serving a plurality of components. Next, a load value corresponding to the plurality of components may be determined. A number of the plurality of power supplies may then be powered down. The number of power supplies powered down may comprise a value that may cause a remaining number of the plurality of power supplies serving the plurality of components to operate within an efficiency range.

A pipeline includes a first portion configured to process a first subset of bits of an instruction and a second portion configured to process a second subset of the bits of the instruction. A first clock mesh is configured to provide a first clock signal to the first portion of the pipeline. A second clock mesh is configured to provide a second clock signal to the second portion of the pipeline. The first and second clock meshes selectively provide the first and second clock signals based on characteristics of in-flight instructions that have been dispatched to the pipeline but not yet retired. In some cases, a physical register file is configured to store values of bits representative of instructions. Only the first subset is stored in the physical register file in response to the value of the zero high bit indicating that the second subset is equal to zero.

A sensing system includes a wireless sensor configured to detect a current sensed value of an environmental condition, the wireless sensor programmed with a delta threshold; a thermostat in communication with the wireless sensor; wherein, when the current sensed value differs from a prior transmitted sensed value by more than the delta threshold, the wireless sensor transmits the current sensed value to the thermostat; wherein, when the current sensed value differs from the prior transmitted sensed value by less than the delta threshold, the wireless sensor stores the current sensed value as a stored sensed value.

A sensing system includes a wireless sensor configured to detect a current sensed value of an environmental condition, the wireless sensor programmed with a delta threshold; a thermostat in communication with the wireless sensor; wherein, when the current sensed value differs from a prior transmitted sensed value by more than the delta threshold, the wireless sensor transmits the current sensed value to the thermostat; wherein, when the current sensed value differs from the prior transmitted sensed value by less than the delta threshold, the wireless sensor stores the current sensed value as a stored sensed value.