A circuit for performing neural network computations for a neural network comprising a plurality of layers, the circuit comprising: activation circuitry configured to receive a vector of accumulated values and configured to apply a function to each accumulated value to generate a vector of activation values; and normalization circuitry coupled to the activation circuitry and configured to generate a respective normalized value from each activation value.

A circuit for performing neural network computations for a neural network comprising a plurality of layers, the circuit comprising: activation circuitry configured to receive a vector of accumulated values and configured to apply a function to each accumulated value to generate a vector of activation values; and normalization circuitry coupled to the activation circuitry and configured to generate a respective normalized value from each activation value.

Shiftable memory employs ring registers to shift a contiguous subset of data words stored in the ring registers within the shiftable memory. A shiftable memory includes a memory having built-in word-level shifting capability. The memory includes a plurality of ring registers to store data words. A contiguous subset of data words is shiftable between sets of the ring registers of the plurality from a first location to a second location within the memory. The contiguous subset of data words has a size that is smaller than a total size of the memory. The memory shifts only data words stored inside the contiguous subset when the contiguous subset is shifted.

Shiftable memory employs ring registers to shift a contiguous subset of data words stored in the ring registers within the shiftable memory. A shiftable memory includes a memory having built-in word-level shifting capability. The memory includes a plurality of ring registers to store data words. A contiguous subset of data words is shiftable between sets of the ring registers of the plurality from a first location to a second location within the memory. The contiguous subset of data words has a size that is smaller than a total size of the memory. The memory shifts only data words stored inside the contiguous subset when the contiguous subset is shifted.

Techniques are disclosed for power conservation. A plurality of processing elements and a plurality of instructions are configured. The plurality of processing elements is controlled by instructions contained in a plurality of circular buffers. The plurality of processing elements can comprise a dataflow processor. A first processing element, from the plurality of interconnected processing elements, is set into a sleep state by a first instruction from the plurality of instructions. The first processing element is woken from the sleep state as a result of valid data being presented to the first processing element. A subsection of the plurality of interconnected processing elements is also set into a sleep state based on the first processing element being set into a sleep state. At least one circular buffer from the plurality of circular buffers remains awake while the first processing element is in the sleep state, and the at least one circular buffer provides for data steering through a reconfigurable fabric.

A hand operated computer input device comprising a main body with a flat support surface for the entire palm heel is provided. The new support surface provided is not for the palm, metacarpals, proximal and intermediate finger segments, or wrist. Only a user's palm heel and finger tips touch the input device. The entire palm heel wholly supports the weight of a users hand and arm. There is no pressure on the median nerve at the wrist or in the hand. There is no angle at the wrist while the hand maintains a generally neutral position. The height between the top of the palm heel support surface and the top surface of the buttons, wheels, etc. places the hand in a generally neutral, relaxed cupped position. The present invention seeks to prevent repetitive strain injury (RSI) and Carpal Tunnel Syndrome while using a horizontal or vertical hand operated computer input device.

A group of low-level FIFOs may be logically bound together to form a super-FIFO. The super-FIFO may treat each low-level FIFO as a storage location. The super-FIFO may enable a push to (or a pop from) every low-level FIFO, simultaneously. The super-FIFO may enable a virtual channel (VC) to use the super-FIFO, bypassing a VC FIFO for the VC, removing several cycles of latency otherwise needed for enqueuing and dequeuing messages in the VC FIFO. In addition, the super-FIFO may enable bypassing of an arbiter, further reducing latency by avoiding a penalty of the arbiter.

An object of the present invention is to prevent occurrence of data destruction when a transfer source region and a transfer destination region of data overlap with each other and even when transfer is performed using a burst transfer function. The data read from the transfer source region is temporarily written into a ring buffer, and then the data written into the ring buffer is written into the transfer source region. In this case, reading of the data from the ring buffer is controlled, based on a magnitude relation between the number of times of wrap-arounds caused by writing of the data into the ring buffer and the number of times of wrap-arounds caused by reading of the data from the ring buffer.

According to one embodiment, a shift register memory includes blocks and a control circuit. The blocks each includes data storing shift strings. Each of the data storing shift strings includes layers. The control circuit performs storing and reading data by shifting one layer of the layers, in a direction along each of the data storing shift strings. The reading includes reading data from a first layer of the layers. The storing includes storing data to a second layer of the layers. The control circuit reads first data stored in one or more third layers of the layers, the one or more third layers being successive from the first layer, determines a shift parameter in accordance with the reading of the first data, and performs the reading using the determined shift parameter.

Embodiments of the invention relate to methods and systems for processing a network data block. One or more embodiments of the invention include receiving network data at a receiver/transmitter comprising a serializer/deserializer (SERDES). One or more embodiments of the invention include identifying, by the PHY, a start of a data block within the network data. One or more embodiments of the invention include performing, by the SERDES and after identifying the start of the data block, a SERDES action to obtain a SERDES data block. In one or more embodiments of the invention, the SERDES action is based on an encoding scheme used in transmission of the network data. One or more embodiments of the invention include also includes transmitting the SERDES data block towards a receiver.