A data bus includes process elements and a linear main pipeline. Each process element is coupled to a linear pipeline having M stages arranged in series, each of the M stages including a buffer element configured to buffer a data bit sequence and to forward the buffered data bit sequence from a first of the buffer elements to a last of the buffer elements. The linear main pipeline includes N pipeline stage elements arranged in series. Each pipeline stage element is connected to the last buffer element of a respective linear pipeline and configured to read-out one or more of the buffered data bit sequences and to forward the read-out data bit sequences from one of N pipeline stag elements to a next of the N pipeline stage elements.

Systems, circuits, and methods for clock domain crossing for an interface between logic circuits are provided. A circuit is configured to allow an exchange of signals between a first logic circuit clocked using a first clock signal having a first frequency and a second logic circuit clocked using a second clock signal having a second frequency different from the first frequency. The circuit includes a first circuit segment configured to receive a first control signal to select the second logic circuit and a second control signal to indicate an initiation of an access operation, and ensure that the second control signal maintains a relationship with the first control signal based on the second clock signal. The circuit further includes a second circuit segment configured to receive, from the second logic circuit, a third control signal indicating a readiness of the second logic circuit to complete the access operation.

Methods and systems for encoding digital information in nucleic acid (e.g., deoxyribonucleic acid) molecules without base-by-base synthesis, by encoding bit-value information in the presence or absence of unique nucleic acid sequences within a pool, comprising specifying each bit location in a bit-stream with a unique nucleic sequence and specifying the bit value at that location by the presence or absence of the corresponding unique nucleic acid sequence in the pool. But, more generally, specifying unique bytes in a bytestream by unique subsets of nucleic acid sequences. Also disclosed are methods for generating unique nucleic acid sequences without base-by-base synthesis using combinatorial genomic strategies (e.g., assembly of multiple nucleic acid sequences or enzymatic-based editing of nucleic acid sequences).

Embodiments of the invention relate to methods and systems for processing a network data block. One or more embodiments of the invention include receiving network data at a receiver/transmitter comprising a serializer/deserializer (SERDES). One or more embodiments of the invention include identifying, by the PHY, a start of a data block within the network data. One or more embodiments of the invention include performing, by the SERDES and after identifying the start of the data block, a SERDES action to obtain a SERDES data block. In one or more embodiments of the invention, the SERDES action is based on an encoding scheme used in transmission of the network data. One or more embodiments of the invention include also includes transmitting the SERDES data block towards a receiver.

Embodiments of the invention relate to methods and systems for processing a network data block. One or more embodiments of the invention include receiving network data at a receiver/transmitter comprising a serializer/deserializer (SERDES). One or more embodiments of the invention include identifying, by the PHY, a start of a data block within the network data. One or more embodiments of the invention include performing, by the SERDES and after identifying the start of the data block, a SERDES action to obtain a SERDES data block. In one or more embodiments of the invention, the SERDES action is based on an encoding scheme used in transmission of the network data. One or more embodiments of the invention include also includes transmitting the SERDES data block towards a receiver.

A configurable circuit configurable according to the data width of elements of a matrix is described that includes a memory array, logic to write a matrix to the memory array having elements with a data width which can be specified using configuration data, logic for a transpose read of the matrix as-written and logic for normal read of the matrix as-written. The memory array includes first and second read ports operable in parallel. Transpose read logic and normal read logic can be coupled to the first and second read ports, respectively, allowing transpose and normal read of a matrix simultaneously.

A configurable circuit configurable according to the data width of elements of a matrix is described that includes a memory array, logic to write a matrix to the memory array having elements with a data width which can be specified using configuration data, logic for a transpose read of the matrix as-written and logic for normal read of the matrix as-written. The memory array includes first and second read ports operable in parallel. Transpose read logic and normal read logic can be coupled to the first and second read ports, respectively, allowing transpose and normal read of a matrix simultaneously.

Input/output (I/O) operation requests from pageable storage mode guests are interpreted without host intervention. In a pageable mode virtual environment, requests issued by pageable storage mode guests are processed by one or more processors of the environment absent intervention from one or more hosts of the environment. Processing of the requests includes manipulating, by at least one processor on behalf of the guests, buffer state information stored in host storage. The manipulating is performed via instructions initiated by the guests and processed by one or more of the processors.

Input/output (I/O) operation requests from pageable storage mode guests are interpreted without host intervention. In a pageable mode virtual environment, requests issued by pageable storage mode guests are processed by one or more processors of the environment absent intervention from one or more hosts of the environment. Processing of the requests includes manipulating, by at least one processor on behalf of the guests, buffer state information stored in host storage. The manipulating is performed via instructions initiated by the guests and processed by one or more of the processors.

A method including receiving, by a processor, a computing instruction for a neural network, wherein the computing instruction for the neural network includes a computing rule for the neural network and a connection weight of the neural network, and the connection weight is a power of 2; and inputting, for a multiplication operation in the computing rule for the neural network, a source operand corresponding to the multiplication operation to a shift register, and performing a shift operation based on a connection weight corresponding to the multiplication operation, wherein the shift register outputs a target result operand as a result of the multiplication operation. The neural network uses a shift operation, and a neural network computing speed is increased.