G06F5/10

See-through computer display systems

Embodiments include a head-worn display including a display panel sized and positioned to produce a field of view to present digital content to an eye of a user, and a processor adapted to present the digital content to the display panel such that the digital content is only presented in a portion of the field of view, the portion being in the middle of the field of view such that horizontally opposing edges of the field of view are blank areas. The processor is adapted to shift the digital content into one of the blank areas to adjust the convergence distance of the digital content and thereby change the perceived distance from the user to the digital content.

See-through computer display systems

Embodiments include a head-worn display including a display panel sized and positioned to produce a field of view to present digital content to an eye of a user, and a processor adapted to present the digital content to the display panel such that the digital content is only presented in a portion of the field of view, the portion being in the middle of the field of view such that horizontally opposing edges of the field of view are blank areas. The processor is adapted to shift the digital content into one of the blank areas to adjust the convergence distance of the digital content and thereby change the perceived distance from the user to the digital content.

Buffer memory, and computation device and system using the same

A computation device includes a buffer memory which provides first to b input feature sets to the computation unit. The buffer memory includes first to n.sup.th memories, and configured to divide and store the first to n.sup.th input feature sets each including a plurality of features in the first to n.sup.th memories, respectively. The plurality of features of one input feature set is divided and stored into the first to n.sup.th memories. Features having the same turn in the first to n.sup.th input feature sets are stored one by one in the first to n.sup.th memories.

Buffer memory, and computation device and system using the same

A computation device includes a buffer memory which provides first to b input feature sets to the computation unit. The buffer memory includes first to n.sup.th memories, and configured to divide and store the first to n.sup.th input feature sets each including a plurality of features in the first to n.sup.th memories, respectively. The plurality of features of one input feature set is divided and stored into the first to n.sup.th memories. Features having the same turn in the first to n.sup.th input feature sets are stored one by one in the first to n.sup.th memories.

Associatively indexed circular buffer
11740900 · 2023-08-29 · ·

Some embodiments of the present disclosure provide an associatively indexed circular buffer (ACB). The ACB may be viewed as a dynamically allocatable memory structure that offers in-order data access (say, first-in-first-out, or “FIFO”) or random order data access at a fixed, relatively low latency. The ACB includes a data store of non-contiguous storage. To manage the pushing of data to, and popping data from, the data store, the ACB includes a contiguous pointer generator, a content addressable memory (CAM) and a free pool.

Associatively indexed circular buffer
11740900 · 2023-08-29 · ·

Some embodiments of the present disclosure provide an associatively indexed circular buffer (ACB). The ACB may be viewed as a dynamically allocatable memory structure that offers in-order data access (say, first-in-first-out, or “FIFO”) or random order data access at a fixed, relatively low latency. The ACB includes a data store of non-contiguous storage. To manage the pushing of data to, and popping data from, the data store, the ACB includes a contiguous pointer generator, a content addressable memory (CAM) and a free pool.

COMPILE TIME LOGIC FOR INSERTING A BUFFER BETWEEN A PRODUCER OPERATION UNIT AND A CONSUMER OPERATION UNIT IN A DATAFLOW GRAPH

A dataflow graph for an application has operation units that are configured to be producers and consumers of tensors. A write access pattern of a particular producer specifies an order in which the particular producer generates elements of a tensor, and a read access pattern of a corresponding consumer specifies an order in which the corresponding consumer processes the elements of the tensor. The technology disclosed detects conflicts between the producers and the corresponding consumers that have mismatches between the write access patterns and the read access patterns. A conflict occurs when the order in which the particular producer generates the elements of the tensor is different from the order in which the corresponding consumer processes the elements of the tensor. The technology disclosed resolves the conflicts by inserting buffers between the producers and the corresponding consumers.

RE-ORDERED PROCESSING OF READ REQUESTS
20220129464 · 2022-04-28 · ·

A method includes determining, in accordance with a first ordering, a plurality of read requests for a memory device. The plurality of read requests are added to a memory device queue for the memory device in accordance with the first ordering. The plurality of read requests in the memory device queue are processed, in accordance with a second ordering that is different from the first ordering, to determine read data for each of the plurality of read requests. The read data for the each of the plurality of read requests is added one of a set of ordered positions, based on the first ordering, of a ring buffer as the each of the plurality of reads requests is processed. The read data of a subset of the plurality of read requests is submitted based on adding the read data to a first ordered position of the set of ordered positions of the ring buffer.

Memory circuit device including a selection circuit unit shared by a write circuit unit and a read circut unit

A memory circuit device includes multiple memory cells that are each constituted of a resistive memory element; a write circuit unit that is configured to write data to any one of the memory cells which is designated by cell designating information, and a read circuit unit that is configured to read out, from the memory cell designated by the cell designating information, data written in the memory cell. The memory circuit device has a configuration including a selection circuit unit that is shared by both of the write circuit unit and the read circuit unit and configured to select a memory cell to be activated from the multiple memory cells based on cell designating information, and a control circuit unit that is configured to selectively enable any one of writing of data by the write circuit unit and reading of data by the read circuit unit with respect to the memory cell selected by the selection circuit unit.

Stray light suppression for head worn computing

Aspects of the present disclosure relate to a computer display stray-light suppression system for a head-worn computer comprising an eye cover including a flexible material with a perimeter, wherein the perimeter is formed to substantially encapsulate an eye of a person, and the eye cover including an attachment system adapted to removably and replaceably attach to a perimeter of the head-worn computer to suppress light emitted from a computer display in the head-worn computer.