The invention proposes a method for dividing archived data based on persistent queue (PQ), including i) dividing this stored data into persistent data queues corresponding to the time it needs to be processed in the future; ii) scheduling the processing of data that has been split into these persistent data queues corresponding to future milestones; and iii) redistribute stored data into new sustainable data queues corresponding to the next time it takes for further processing of this data.

Multiple listlets function as a single master linked list to manage data packets across one or more banks of memory in a first-in first-out (FIFO) order, while allowing multiple push and/or pop functions to be performed per cycle. Each listlet can be a linked list that tracks pointers and is stored in a different memory bank. The nodes can include a pointer to a data packet, a pointer to the next node in the listlet and a next listlet identifier that identifies the listlet that contains the next node in the master linked list. The head and tail of each listlet, as well as an identifier each to track the head and tail of the master linked list, can be maintained in cache. The individual listlets are updated accordingly to maintain order of the master linked list as pointers are pushed and popped from the master linked list.

Multiple listlets function as a single master linked list to manage data packets across one or more banks of memory in a first-in first-out (FIFO) order, while allowing multiple push and/or pop functions to be performed per cycle. Each listlet can be a linked list that tracks pointers and is stored in a different memory bank. The nodes can include a pointer to a data packet, a pointer to the next node in the listlet and a next listlet identifier that identifies the listlet that contains the next node in the master linked list. The head and tail of each listlet, as well as an identifier each to track the head and tail of the master linked list, can be maintained in cache. The individual listlets are updated accordingly to maintain order of the master linked list as pointers are pushed and popped from the master linked list.

There is provided with an information processing apparatus. A control unit controls writing of weight data to a first memory and a second memory, and controls readout of the weight data from the first memory and the second memory. The control unit further switches an operation between a first operation in which a processing unit reads out first weight data from the first memory and performs the convolution operation processing using the first weight data while the processing unit writes second weight data to the second memory in parallel, and a second operation in which the processing unit reads out the first weight data from both the first memory and the second memory and performs the convolution operation processing using the first weight data.

An enhanced dynamic random access memory (eDRAM)-based computing-in-memory (CIM) convolutional neural network (CNN) accelerator comprises four P2ARAM blocks, where each of the P2ARAM blocks includes a 5T1C ping-pong eDRAM bit cell array composed of 6416 5T1C ping-pong eDRAM bit cells. In each of the P2ARAM blocks, 642 digital time converters convert a 4-bit activation value into different pulse widths from a row direction and input the pulse widths into the 5T1C ping-pong eDRAM bit cell array for calculation. A total of 162 convolution results are output in a column direction of the 5T1C ping-pong eDRAM bit cell array. The CNN accelerator uses the 5T1C ping-pong eDRAM bit cells to perform multi-bit storage and convolution in parallel. An S2M-ADC scheme is proposed to allot an area of an input sampling capacitor of an ABL to sign-numerical SAR ADC units of a C-DAC array without adding area overhead.

An enhanced dynamic random access memory (eDRAM)-based computing-in-memory (CIM) convolutional neural network (CNN) accelerator comprises four P2ARAM blocks, where each of the P2ARAM blocks includes a 5T1C ping-pong eDRAM bit cell array composed of 6416 5T1C ping-pong eDRAM bit cells. In each of the P2ARAM blocks, 642 digital time converters convert a 4-bit activation value into different pulse widths from a row direction and input the pulse widths into the 5T1C ping-pong eDRAM bit cell array for calculation. A total of 162 convolution results are output in a column direction of the 5T1C ping-pong eDRAM bit cell array. The CNN accelerator uses the 5T1C ping-pong eDRAM bit cells to perform multi-bit storage and convolution in parallel. An S2M-ADC scheme is proposed to allot an area of an input sampling capacitor of an ABL to sign-numerical SAR ADC units of a C-DAC array without adding area overhead.

Multiple listlets function as a single master linked list to manage data packets across one or more banks of memory in a first-in first-out (FIFO) order, while allowing multiple push and/or pop functions to be performed per cycle. Each listlet can be a linked list that tracks pointers and is stored in a different memory bank. The nodes can include a pointer to a data packet, a pointer to the next node in the listlet and a next listlet identifier that identifies the listlet that contains the next node in the master linked list. The head and tail of each listlet, as well as an identifier each to track the head and tail of the master linked list, can be maintained in cache. The individual listlets are updated accordingly to maintain order of the master linked list as pointers are pushed and popped from the master linked list.

Multiple listlets function as a single master linked list to manage data packets across one or more banks of memory in a first-in first-out (FIFO) order, while allowing multiple push and/or pop functions to be performed per cycle. Each listlet can be a linked list that tracks pointers and is stored in a different memory bank. The nodes can include a pointer to a data packet, a pointer to the next node in the listlet and a next listlet identifier that identifies the listlet that contains the next node in the master linked list. The head and tail of each listlet, as well as an identifier each to track the head and tail of the master linked list, can be maintained in cache. The individual listlets are updated accordingly to maintain order of the master linked list as pointers are pushed and popped from the master linked list.

One embodiment of the present invention sets forth a data pipeline, which includes a first mousetrap element and a second mousetrap element in a first pipeline stage. Each mousetrap element includes a request latch that, when enabled, allows a request signal to pass from the first pipeline stage to a second pipeline stage following the first pipeline stage in the data pipeline. Each mousetrap element also includes a data latch that, when enabled, allows a data element to pass from the first pipeline stage to the second pipeline stage. Each mousetrap element further includes a latch controller that enables and disables the request and data latches based on a phase signal that alternates between a first value that configures the first mousetrap element to transmit data to the second pipeline stage and a second value that configures the second mousetrap element to transmit data to the second pipeline stage.

One embodiment of the present invention sets forth a data pipeline, which includes a first mousetrap element and a second mousetrap element in a first pipeline stage. Each mousetrap element includes a request latch that, when enabled, allows a request signal to pass from the first pipeline stage to a second pipeline stage following the first pipeline stage in the data pipeline. Each mousetrap element also includes a data latch that, when enabled, allows a data element to pass from the first pipeline stage to the second pipeline stage. Each mousetrap element further includes a latch controller that enables and disables the request and data latches based on a phase signal that alternates between a first value that configures the first mousetrap element to transmit data to the second pipeline stage and a second value that configures the second mousetrap element to transmit data to the second pipeline stage.