A computer-implemented method for organizing tasks presented on a graphical user interface of a computer hardware system for a user includes the following operations. An electronic message associated with a collaborative messaging application executing with the computer hardware system is received. A first collaboration having one or more collaborative tasks is identified from the electronic message. A need-for-action, a time-to-act, and a time-to-complete are determined for the first collaboration. A moving average for the first collaboration is adjusted based upon the need-for-action, the time-to-action, and a time-to-complete. The presentation of the first collaboration within the graphical user interface is altered based upon the moving average.

A computer-implemented method for organizing tasks presented on a graphical user interface of a computer hardware system for a user includes the following operations. An electronic message associated with a collaborative messaging application executing with the computer hardware system is received. A first collaboration having one or more collaborative tasks is identified from the electronic message. A need-for-action, a time-to-act, and a time-to-complete are determined for the first collaboration. A moving average for the first collaboration is adjusted based upon the need-for-action, the time-to-action, and a time-to-complete. The presentation of the first collaboration within the graphical user interface is altered based upon the moving average.

Provided herein may be a memory controller configured to control a memory device. The memory controller may include a map buffer, a descriptor queue, and a descriptor controller. The map buffer may sequentially store map segments of a plurality of map segments stored in the memory device. The descriptor queue may store descriptors corresponding to the respective map segments, based on a plurality of addresses of the map buffer. The descriptor controller may search for a target descriptor among the stored descriptors based on a logical address received from a host, and reorder the stored descriptors while searching for the target descriptor.

Provided herein may be a memory controller configured to control a memory device. The memory controller may include a map buffer, a descriptor queue, and a descriptor controller. The map buffer may sequentially store map segments of a plurality of map segments stored in the memory device. The descriptor queue may store descriptors corresponding to the respective map segments, based on a plurality of addresses of the map buffer. The descriptor controller may search for a target descriptor among the stored descriptors based on a logical address received from a host, and reorder the stored descriptors while searching for the target descriptor.

A method of selecting, in hardware logic, an i.sup.th largest or a p.sup.th smallest number from a set of n m-bit numbers is described. The method is performed iteratively and in the r.sup.th iteration, the method comprises: summing an (m−r).sup.th bit from each of the m-bit numbers to generate a summation result and comparing the summation result to a threshold value. Depending upon the outcome of the comparison, the r.sup.th bit of the selected number is determined and output and additionally the (m−r−1).sup.th bit of each of the m-bit numbers is selectively updated based on the outcome of the comparison and the value of the (m−r).sup.th bit in the m-bit number. In a first iteration, a most significant bit from each of the m-bit numbers is summed and each subsequent iteration sums bits occupying successive bit positions in their respective numbers.

A method of selecting, in hardware logic, an i.sup.th largest or a p.sup.th smallest number from a set of n m-bit numbers is described. The method is performed iteratively and in the r.sup.th iteration, the method comprises: summing an (m−r).sup.th bit from each of the m-bit numbers to generate a summation result and comparing the summation result to a threshold value. Depending upon the outcome of the comparison, the r.sup.th bit of the selected number is determined and output and additionally the (m−r−1).sup.th bit of each of the m-bit numbers is selectively updated based on the outcome of the comparison and the value of the (m−r).sup.th bit in the m-bit number. In a first iteration, a most significant bit from each of the m-bit numbers is summed and each subsequent iteration sums bits occupying successive bit positions in their respective numbers.

An image processing apparatus and an image processing method make it possible to suppress increase of the load of template matching. For each of motion vector candidates of accuracy rougher than accuracy of a motion vector candidate list, template matching between a template of a current block and a template of a reference block is performed to derive a cost, and elements of the motion vector candidate list are sorted on the basis of the derived costs of the motion vector candidates. Alternatively, for each of motion vector candidates of accuracy rougher than accuracy of a motion vector candidate list, template matching between a template of a current block and a template of a search point is performed to derive a cost, and a modification motion vector candidate is derived on the basis of the derived costs of the motion vector candidates.

An image processing apparatus and an image processing method make it possible to suppress increase of the load of template matching. For each of motion vector candidates of accuracy rougher than accuracy of a motion vector candidate list, template matching between a template of a current block and a template of a reference block is performed to derive a cost, and elements of the motion vector candidate list are sorted on the basis of the derived costs of the motion vector candidates. Alternatively, for each of motion vector candidates of accuracy rougher than accuracy of a motion vector candidate list, template matching between a template of a current block and a template of a search point is performed to derive a cost, and a modification motion vector candidate is derived on the basis of the derived costs of the motion vector candidates.

A data processing apparatus in which a trade-off between over-learning prevention and calculation load prevention is eliminated when creating a model formula is provided. The data processing apparatus includes: a recording unit that records electronic data; and a computing unit that performs computing using the electronic data, in which the computing unit includes a feature amount selection unit used for computing, and the feature amount selection unit performs feature amount selection including: a first step (S101) of ranking feature amounts and rearranging the feature amounts from top; a second step (S103) of creating a plurality of data groups using only a part of the feature amounts according to the order; a third step (S104) of calculating a value that is an index for evaluating prediction performance of a regression or classification problem using each of the data groups using only a part of the feature amounts; a fourth step (S105) of deleting feature amounts based on the calculated prediction performance index; and a fifth step (S106) of updating the order of the feature amounts, which are feature amounts other than the deleted feature amount, using the prediction performance index, in which the second step to the fifth steps are iterated (S102) until an optimal value of the prediction performance index calculated in the third step is no longer updated.

A data processing apparatus in which a trade-off between over-learning prevention and calculation load prevention is eliminated when creating a model formula is provided. The data processing apparatus includes: a recording unit that records electronic data; and a computing unit that performs computing using the electronic data, in which the computing unit includes a feature amount selection unit used for computing, and the feature amount selection unit performs feature amount selection including: a first step (S101) of ranking feature amounts and rearranging the feature amounts from top; a second step (S103) of creating a plurality of data groups using only a part of the feature amounts according to the order; a third step (S104) of calculating a value that is an index for evaluating prediction performance of a regression or classification problem using each of the data groups using only a part of the feature amounts; a fourth step (S105) of deleting feature amounts based on the calculated prediction performance index; and a fifth step (S106) of updating the order of the feature amounts, which are feature amounts other than the deleted feature amount, using the prediction performance index, in which the second step to the fifth steps are iterated (S102) until an optimal value of the prediction performance index calculated in the third step is no longer updated.