Various implementations of sorting networks are described that utilize time-encoded data signals having encoded values. In some examples, an electrical circuit device includes a sorting network configured to receive a plurality of time-encoded signals. Each time-encoded signal of the plurality of time-encoded signals encodes a data value based on a duty cycle of the respective time-encoded signal or based on a proportion of data bits in the respective time-encoded signal that are high relative to the total data bits in the respective time-encoded signal. The sorting network is also configured to sort the plurality of time-encoded signals based on the encoded data values of the plurality of time-encoded signals.

Apparatuses, systems, and techniques are presented to select neural networks. In at least one embodiment, one or more first neural networks can be used to select one or more second neural networks, as may be based at least in part upon an inference to be generated by the one or more second neural networks.

Apparatuses, systems, and techniques are presented to select neural networks. In at least one embodiment, one or more first neural networks can be used to select one or more second neural networks, as may be based at least in part upon an inference to be generated by the one or more second neural networks.

An electronic apparatus and a method for reducing the number of commands are provided. The electronic apparatus includes a central processor and a co-processor. The central processor generates a plurality of original register setting commands to set at least one bit of at least one register of the co-processor. The original register setting commands include a plurality of first original register setting commands, and a plurality of setting targets of the first original register setting commands have address continuity. The central processor merges the first original register setting commands to generate at least one merged register setting command. The central processor transmits the at least one merged register setting command to the co-processor.

A method of identifying causal relationships between time series may include accessing a hierarchy of nodes in a data structure, where each node in the plurality of nodes may include a time series of data. The method may also include identifying a subset of nodes in the plurality of nodes for which causal relationships may exist in the corresponding time series. The method may additionally include generating a model for each of the subset of nodes, where the model may receive the subset of nodes and generate coefficients indicating how strongly each of the subset of nodes causally affects other nodes in the subset of nodes. The method may further include generating a ranked output of nodes that causally affect a first node in the subset of nodes based on an output of the corresponding model.

Methods, apparatus, systems, and articles of manufacture are disclosed to decode receipts based on neural graph architecture. An example apparatus for decoding receipts includes, vertex feature representation circuitry to extract features from optical-character-recognition (OCR) words, polar coordinate circuitry to: calculate polar coordinates of the OCR words based on respective ones of the extracted features, graph neural network circuitry to generate an adjacency matrix based on the extracted features, post-processing circuitry to traverse the adjacency matrix to generate cliques of OCR processed words, and output circuitry to generate lines of text based on the cliques of OCR processed words.

Methods, apparatus, systems, and articles of manufacture are disclosed to decode receipts based on neural graph architecture. An example apparatus for decoding receipts includes, vertex feature representation circuitry to extract features from optical-character-recognition (OCR) words, polar coordinate circuitry to: calculate polar coordinates of the OCR words based on respective ones of the extracted features, graph neural network circuitry to generate an adjacency matrix based on the extracted features, post-processing circuitry to traverse the adjacency matrix to generate cliques of OCR processed words, and output circuitry to generate lines of text based on the cliques of OCR processed words.

A technique for scheduling instructions includes obtaining a set of instructions that operate on memory objects, and determining the dependencies of the memory objects. The memory objects are then sorted into a sequence of memory objects based on the dependencies of the memory objects, and the set of instructions are scheduled into a sequence of instructions according to the sequence of memory objects. Sorting memory objects allows instructions that operate on the same memory object to be kept together. This helps minimize spilling conditions because intervening instructions that do not operate on the same memory object can be avoided.

A technique for scheduling instructions includes obtaining a set of instructions that operate on memory objects, and determining the dependencies of the memory objects. The memory objects are then sorted into a sequence of memory objects based on the dependencies of the memory objects, and the set of instructions are scheduled into a sequence of instructions according to the sequence of memory objects. Sorting memory objects allows instructions that operate on the same memory object to be kept together. This helps minimize spilling conditions because intervening instructions that do not operate on the same memory object can be avoided.

Systems and methods including one or more processors and one or more non-transitory storage devices storing computing instructions configured to run on the one or more processors and perform: executing a greedy incremental batcher loop, which can comprise: selecting a first picklist of one or more picklists; and merging the first picklist with one or more picklists in a first remainder of the one or more picklists when the merging would decrease a cost of the first picklist, wherein the first remainder of the one or more picklists comprises the one or picklists excluding the first picklist; executing a randomized tote local search loop, which can comprise: selecting two random picklists of the one or more picklists, as merged; and swapping totes of the two random picklists of the one or more picklists, as merged, when the swapping would decrease a cost of at least one picklist of the two random picklists; executing an update min trolley loop, which can comprise: selecting a shortest picklist of the one or more picklists, as merged and swapped; and combining the shortest picklist with at least one picklist of the one or more picklists, as merged and swapped, wherein a combination picklist of the shortest picklist and the at least one picklist results in a savings of cost; and facilitating displaying the combination picklist and the one or more picklists, as merged and swapped, to a picker. Other embodiments are disclosed herein.