A neural network circuit that uses a ramp function as an activation function includes a memory device in which memristors serving as memory elements are connected in a matrix. The neural network circuit further includes I-V conversion amplification circuits for converting currents flowing via the memory elements into voltages, a differential amplifier circuit for performing a differential operation on outputs of two I-V conversion amplification circuits, an A-D converter for performing an A-D conversion on a result of the differential operation, and an output determine that, by referring to input signals of the differential amplifier circuit, determines whether an output signal value of the differential amplifier circuit belongs to an active region or an inactive region. Based on a determination result, the input determiner switches over the differential amplifier circuit and the A-D converter between an operating state and a standby state.

According to examples, an apparatus may include an arithmetic logic unit (ALU) to apply a modification function to a digital input signal to generate a modified digital input signal, a digital-to-analog converter (DAC) to convert the modified digital input signal to an analog input signal, a crossbar array to apply an operation on the analog input signal to generate an analog output signal, and an analog-to-digital converter (ADC). The ADC may modify the analog output signal to compensate for application of the modification function to the digital input signal, may convert the modified analog output signal to a digital output signal, and may output the digital output signal.

Systems and methods for creating mechanical computing mechanisms and Turing-complete systems which include combinatorial logic and sequential logic, and are energy-efficient.

According to examples, an apparatus may include an arithmetic logic unit (ALU) to apply a modification function to a digital input signal to generate a modified digital input signal, a digital-to-analog converter (DAC) to convert the modified digital input signal to an analog input signal, a crossbar array to apply an operation on the analog input signal to generate an analog output signal, and an analog-to-digital converter (ADC). The ADC may modify the analog output signal to compensate for application of the modification function to the digital input signal, may convert the modified analog output signal to a digital output signal, and may output the digital output signal.

An array of variable resistance cells based on a programmable threshold transistor and a resistor connected in parallel is described, including 3D and split gate variations. An input voltage applied to the transistor, and the programmable threshold of the transistor, can represent variables of sum-of-products operations. Programmable threshold transistors in the variable resistance cells comprise charge trapping memory transistors, such as floating gate transistors or dielectric charge trapping transistors. The resistor in the variable resistance cells can comprise a buried implant resistor connecting the current-carrying terminals (e.g. source and drain) of the programmable threshold transistor. A voltage sensing sense amplifier is configured to sense the voltage generated by the variable resistance cells as a function of an applied current and the resistance of the variable resistance cells.

According to an embodiment, a neural network device includes a control unit, and a matrix computation unit. The control unit causes a plurality of layers to execute a forward process of propagating a plurality of signal values in a forward direction, and a backward process of propagating a plurality of error values in a backward direction. The matrix computation unit performs computation on a plurality of values propagated in the plurality of layers. The matrix computation unit includes (mn) multipliers, and an addition circuit. The (mn) multipliers are provided in one-to-one correspondence with (mn) coefficients included in a coefficient matrix of m rows and n columns. The addition circuit switches a pattern for adding values output from the respective (mn) multipliers between the forward process and the backward process.

A resettable mechanical logic circuit is disclosed which is formed as part of a material structure. The circuit makes use of a bistable element. The bistable element may have a characteristic of being stable in either one of first and second orientations, once moved past a midpoint between the first and second orientations.

A resettable mechanical logic circuit is disclosed which is formed as part of a material structure. The circuit makes use of a bistable element. The bistable element may have a characteristic of being stable in either one of first and second orientations, once moved past a midpoint between the first and second orientations.

Systems and methods for creating mechanical computing mechanisms and Turing-complete systems which include combinatorial logic and sequential logic, and are energy-efficient.

A reservoir computer. In some embodiments, the reservoir computer includes a Duffing oscillator, and a readout circuit, and the readout circuit is configured to calculate a plurality of products, each of the products being calculated by multiplying a sample, of a plurality of samples of a signal from the Duffing oscillator, by a respective weight of a plurality of weights.