The present invention discloses a computing array based on 1T1R device, operation circuits and operating methods thereof. The computing array has 1T1R arrays and a peripheral circuit; the 1T1R array is configured to achieve operation and storage of an operation result, and the peripheral circuit is configured to transmit data and control signals to control operation and storage processes of the 1T1R arrays; the operation circuits are respectively configured to implement a 1-bit full adder, a multi-bit step-by-step carry adder and optimization design thereof, a 2-bit data selector, a multi-bit carry select adder and a multi-bit pre-calculation adder; and in the operating method corresponding to the operation circuit, initialized resistance states of the 1T1R devices, word line input signals, bit line input signals and source line input signals are controlled to complete corresponding operation and storage processes.

Techniques described herein may be utilized to implement methods and systems for lossless compression and serialization of arithmetic circuits to a bit stream using compression techniques such as the arithmetic coding. An arithmetic circuit representing a smart contract may be compressed using arithmetic coding, thereby generating a compressed arithmetic circuit that can be stored or broadcast to a blockchain network using less computational resources (e.g., data storage resources) than would otherwise be needed to store the arithmetic circuit. The arithmetic circuit can be efficiently compressed using entropy coding based on the frequency of elements in the data structure, such as the arithmetic operator types. Instructions for de-serialization and de-compression can also be embedded in the bit stream, and can be used (e.g., by another computer system) to reconstruct the original circuit in a lossless manner.

Techniques described herein may be utilized to implement methods and systems for lossless compression and serialization of arithmetic circuits to a bit stream using compression techniques such as the arithmetic coding. An arithmetic circuit representing a smart contract may be compressed using arithmetic coding, thereby generating a compressed arithmetic circuit that can be stored or broadcast to a blockchain network using less computational resources (e.g., data storage resources) than would otherwise be needed to store the arithmetic circuit. The arithmetic circuit can be efficiently compressed using entropy coding based on the frequency of elements in the data structure, such as the arithmetic operator types. Instructions for de-serialization and de-compression can also be embedded in the bit stream, and can be used (e.g., by another computer system) to reconstruct the original circuit in a lossless manner.

Methods and apparatus for optimizing a quantum circuit. In one aspect, a method includes identifying one or more sequences of operations in the quantum circuit that un-compute respective qubits on which the quantum circuit operates; generating an adjusted quantum circuit, comprising, for each identified sequence of operations in the quantum circuit, replacing the sequence of operations with an X basis measurement and a classically-controlled phase correction operation, wherein a result of the X basis measurement acts as a control for the classically-controlled correction phase operation; and executing the adjusted quantum circuit.

Systems, apparatuses, and methods related to a neuron built with posits are described. An example system may include a memory device and the memory device may include a plurality of memory cells. The plurality of memory cells can store data including a bit string in an analog format. A neuromorphic operation can be performed on the data in the analog format. The example system may include an analog to digital converter coupled to the memory device. The analog to digital converter may convert the bit string in the analog format stored in at least one of the plurality of memory cells to a format that supports arithmetic operations to a particular level of precision.

Systems, apparatuses, and methods related to a neuron built with posits are described. An example system may include a memory device and the memory device may include a plurality of memory cells. The plurality of memory cells can store data including a bit string in an analog format. A neuromorphic operation can be performed on the data in the analog format. The example system may include an analog to digital converter coupled to the memory device. The analog to digital converter may convert the bit string in the analog format stored in at least one of the plurality of memory cells to a format that supports arithmetic operations to a particular level of precision.

Techniques described herein may be utilized to implement methods and systems for lossless compression and serialization of arithmetic circuits to a bit stream using compression techniques such as the arithmetic coding. An arithmetic circuit representing a smart contract may be compressed using arithmetic coding, thereby generating a compressed arithmetic circuit that can be stored or broadcast to a blockchain network using less computational resources (e.g., data storage resources) than would otherwise be needed to store the arithmetic circuit. The arithmetic circuit can be efficiently compressed using entropy coding based on the frequency of elements in the data structure, such as the arithmetic operator types. Instructions for de-serialization and de-compression can also be embedded in the bit stream, and can be used (e.g., by another computer system) to reconstruct the original circuit in a lossless manner.

Techniques described herein may be utilized to implement methods and systems for lossless compression and serialization of arithmetic circuits to a bit stream using compression techniques such as the arithmetic coding. An arithmetic circuit representing a smart contract may be compressed using arithmetic coding, thereby generating a compressed arithmetic circuit that can be stored or broadcast to a blockchain network using less computational resources (e.g., data storage resources) than would otherwise be needed to store the arithmetic circuit. The arithmetic circuit can be efficiently compressed using entropy coding based on the frequency of elements in the data structure, such as the arithmetic operator types. Instructions for de-serialization and de-compression can also be embedded in the bit stream, and can be used (e.g., by another computer system) to reconstruct the original circuit in a lossless manner.

An apparatus with multi-format data support includes: a receiver configured to receive a plurality of data corresponding to a plurality of data formats; one or more processors configured to: multiply the plurality of data using one or more multipliers; perform a first alignment on a result of the multiplication based on an exponent value of the plurality of data; add a result of the first alignment; and perform a second alignment on a result of the addition based on the exponent value and an operation result of a previous cycle.

A fast Fourier transform (FFT) circuit of an audio processing device configured to perform an N-points FFT and including a memory circuit and a butterfly operation unit circuit is provided. The butterfly operation unit circuit reads two points input data from the memory circuit, performs a butterfly operation for the two points input data according to a twiddle factor to generate two points output data, and writes the two points output data into the memory circuit. The butterfly operation unit circuit includes a multiplier and a plurality of adders/subtractors. The multiplier sequentially multiplies real or imaginary coefficients of one of the two points input data by real or imaginary coefficients of the twiddle factor in multiple clock cycles. The multiplier performs a multiplication once in each clock cycle. The adders/subtractors perform addition/subtraction, such that the butterfly operation unit circuit generates the two points output data.