Methods and systems are provided for noise suppression in data, particularly data comprising video and/or audio data. An input adjustment, based on a corresponding input adjustment value, may be applied to received input data that comprises video and/or audio data; and an output adjustment, based on a corresponding output adjustment value, may be applied to output data corresponding to previously processed received input data. The input adjustment value may be re-calculated based on an outcome of applying the input adjustment to the received data, and when a change occurs in the input adjustment value the change in the input adjustment value may be applied to subsequent received input data, and at the same time, and based on the change in the input adjustment value, a corresponding change may be applied at least some of data corresponding to previously processed received input data.

Apparatus, systems, and/or methods may include a peripheral component interconnect express (PCIe) link to directly couple a slot with a network fabric. The slot may be defined by a surface and/or may accommodate a hardware module. A rack unit implementation may be utilized, such as a one rack unit (1 U) implementation, a four rack unit (4 U) implementation, and so on. The network fabric may be utilized when hardware modules communicate across the PCIe link, may be bypassed when hardware modules communicate across an additional PCIe link, and so on. The PCIe link may include a direct connect point-to-point PCIe link, a dual star PCIe link, and so on. In addition, the PCIe link may be utilized in a rack-scale architecture.

A common sub-expression elimination method for simplifying hardware logic of a hardware filter circuit by eliminating a common sub-expression included in a plurality of sub-expressions is provided. Each of the sub-expressions includes a corresponding two or more of inputs constituting a plurality of coefficients used by the hardware filter circuit. The method is implemented on a computing device and includes: identifying for each coefficient of the plurality of coefficients, a combination of the inputs constituting the coefficient; counting occurrences of the sub-expressions in each of the coefficients; identifying one or more of the sub-expressions having a maximum one of the counts and including the corresponding two or more of the inputs; selecting one of the one or more of the sub-expressions as the common sub-expression; eliminating the common sub-expression; and repeating these steps to eliminate more of the sub-expressions common to multiple ones of the coefficients.

An instruction to perform a comparison of a first value and a second value is executed. Based on a control of the instruction, a compare function to be performed is determined. The compare function is one of a plurality of compare functions configured for the instruction, and the compare function has a plurality of options for comparison. A compare option based on the first value and the second value is selected from the plurality of options defined for the compare function, and used to compare the first value and the second value. A result of the comparison is then placed in a select location, the result to be used in processing within a computing environment.

A universal quantum computer may be emulated by a classical computing system that uses an electronic signal of bounded duration and amplitude to represent an arbitrary initial quantum state. The initial quantum state may be specified by inputs provided to the system and may be encoded in the signal, which is derived from a collection of phase-coherent coherent basis signals. Unitary quantum computing gate operations, including logical operations on qubits or operations that change the phase of a qubit, may be performed using analog electronic circuits within the quantum computing emulation device. These circuits, which may apply a matrix transformation to the signals representing the initial quantum state, may include four-quadrant multipliers, operational amplifiers, and analog filters. A measurement component within the quantum computing emulation device may produce a digital signal output representing the transformed quantum state. The gate operation(s) performed may be selected from among multiple supported operations.

Training neural networks by constructing a neural network model having neurons each associated with a quantized activation function adapted to output a quantized activation value. The neurons are arranged in layers and connected by connections associated quantized connection weight functions adapted to output quantized connection weight values. During a training process a plurality of weight gradients are calculated during backpropagation sub-processes by computing neuron gradients, each of an output of a respective the quantized activation function in one layer with respect to an input of the respective quantized activation function. Each neuron gradient is calculated such that when an absolute value of the input is smaller than a positive constant threshold value, the respective neuron gradient is set as a positive constant output value and when the absolute value of the input is smaller than the positive constant threshold value the neuron gradient is set to zero.

A system includes an integrated circuit coupled to the memory. The integrated circuit is configured to receive first and second complex numbers at one or more data inputs. A first value is determined using a first set of product arrays of a first real number multiplier. A second value is determined using a second set of product arrays of the first real number multiplier and a third set of product arrays of a second real number multiplier. A third value is determined using a fourth set of product arrays of the second real number multiplier. A real value of a first product of the first complex number times a second complex number is determined using the first value and the second value. An imaginary value of the first product is determined using the second value and the third value.

In an embodiment, a division circuit has an overflow determination circuit configured to determine whether or not a division result overflows by comparing absolute values of a dividend and a divisor, a replacement circuit configured to replace the dividend with a first value and replace the divisor with a second value when the overflow determination circuit determines that the division result overflows, and a stepwise division circuit configured to perform stepwise division on the dividend and the divisor or the first value and the second value.

Apparatus and method to transform complex data including a processor that comprises: multiplier circuitry to multiply packed complex N-bit data elements with packed complex M-bit data elements to generate at least four real products; adder circuitry to subtract a first real product from a second real product to generate a first temporary result, subtract a third real product from a fourth real product to generate a second temporary result, add the first temporary result to a first packed N-bit data element to generate a first pre-scaled result, subtract the first temporary result from the first packed N-bit data element to generate a second pre-scaled result, add the second temporary result to a second packed N-bit data element to generate a third pre-scaled result, and subtract the second temporary result from the second packed N-bit data element to generate a fourth pre-scaled result; and scaling circuitry to scale the pre-scaled results.

A computer performs generating, on the basis of mathematical expression information indicating a complex function, first display information on a first three-dimensional graph that indicates a relationship between a first variable indicating a real part of a first complex number input to the complex function indicated by the mathematical expression information, a second variable indicating an imaginary part of the first complex number, and a third variable indicating a real part of a second complex number output from the complex function, generating, on the basis of the mathematical expression information, second display information on a second three-dimensional graph that indicates a relationship between the first variable, the second variable, and a fourth variable indicating an imaginary part of the second complex number, and outputting display information including the first display information and the second display information.